Texas Instruments SN74ALS876ANT
- Part No.:
- SN74ALS876ANT
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 24-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74ALS876ANT.pdf
- Description:
- IC FF D-TYPE DUAL 4BIT 24DIP
- Quantity:
- Payment:

- Shipping:

Inventory:3,167
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74ALS876ANT from Texas Instruments is a dual 4-bit D-type edge-triggered flip-flop with inverting 3-state outputs, designed as a bus-oriented register for bidirectional data flow control. It features asynchronous preset (PRE) inputs, true clock-edge triggering (CLK↑), and operates at up to 30 MHz across 0°C to 70°C. It is used in legacy industrial I/O port expansion and buffered address/data latching.
For engineers reviewing the SN74ALS876ANT datasheet, SN74ALS876ANT pinout, SN74ALS876ANT application, or SN74ALS876ANT equivalent, key selection considerations include its inverting Q-output behavior, 24-pin plastic DIP (NT) package, 3-state bus-driving capability, and compatibility with ALS logic family voltage thresholds and timing margins.
Technical Context
This device implements two independent 4-bit D-register sections, each with dedicated clock, preset, output-enable, and data inputs. Each section drives four inverting Q outputs that enter high-impedance state when OE is high - enabling shared-bus arbitration without external gating.
It uses bipolar ALS (Advanced Low-Power Schottky) technology, delivering higher speed than standard LS while maintaining TTL-compatible input thresholds (VIH = 2 V min, VIL = 0.8 V max) and robust 24-mA sink capability per output. Propagation delays are specified from CLK↑ to Q (tPLH/tPHL ≤ 14 ns) and from PRE↓ to Q (tPHL ≤ 19 ns).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | ALS (Advanced Low-Power Schottky) - ensures TTL compatibility with improved speed-power tradeoff vs. LS. |
| Function | Dual 4-bit edge-triggered D-type flip-flop with inverting Q outputs and asynchronous preset - enables synchronized data capture with immediate reset-to-low on PRE assertion. |
| Max Clock Frequency | 30 MHz - supports high-speed bus buffering in legacy microprocessor systems (e.g., Z80, 8085, 68000 peripherals). |
| Output Drive | 24 mA sink / −2.6 mA source - sufficient to directly drive multiple TTL loads or terminate unterminated buses. |
| Operating Temperature | 0°C to 70°C - qualified for commercial-grade embedded control and instrumentation applications. |
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5-V logic rails; absolute max rating is 7 V. |
| Propagation Delay | tPLH/tPHL ≤ 14 ns (CLK↑ to Q) - ensures tight timing alignment in synchronous register chains. |
Pinout & Package
SN74ALS876ANT is housed in a 24-pin plastic dual-in-line package (DIP), designated NT by Texas Instruments. The package has 300-mil width, through-hole mounting, and standard DIP pin spacing (0.1 inch).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | 1PRE / 2PRE | Asynchronous active-low preset - forces corresponding Q1–Q4 outputs low regardless of clock state. |
| 2, 14 | 1OE / 2OE | Active-low 3-state output enable - disables all four Q outputs of respective section into high-Z. |
| 3–6, 7–10 | 1D1–1D4 / 2D1–2D4 | Data inputs for each 4-bit register section - sampled on rising CLK edge. |
| 11, 23 | 1CLK / 2CLK | Positive-edge-triggered clock inputs - controls synchronous loading of D inputs to Q outputs. |
| 12 | GND | Ground reference for all internal circuitry and output drivers. |
| 24 | VCC | +5 V supply rail - powers all logic and output stages; decoupling required near pin. |
| 15–18, 19–22 | 2Q1–2Q4 / 1Q1–1Q4 | Inverting 3-state outputs - reflect complement of loaded D values when OE is low and PRE is high. |
Key Features
| Feature | Design Value |
|---|---|
| Bus-structured pinout | Enables direct PCB routing to parallel data/address buses without signal crossing - reduces layout complexity in backplane and motherboard designs. |
| Inverting Q outputs | Eliminates need for external inverters when interfacing with active-low control signals or complement-based bus protocols. |
| Asynchronous preset (PRE) | Allows immediate initialization of register contents to logic low without waiting for next clock edge - critical for power-on reset and fault recovery. |
| 3-state output control (OE) | Permits multiple SN74ALS876ANT devices to share a common data bus - essential for I/O port expansion and memory-mapped peripheral interfaces. |
| ALS logic family performance | Delivers 30 MHz operation with 14 ns propagation delay and 24 mA sink strength - exceeds standard LS while consuming less power than AS. |
Applications
| Industrial PLC I/O Expansion | Legacy Microprocessor Address Latching |
|---|---|
Use Scenario: Adding parallel digital input/output capability to programmable logic controllers using discrete TTL/ALS logic. IC Role / Device Role / Timing Role: Acts as a buffered, presettable 8-bit I/O port register - captures sensor status or drives actuators under CPU control via shared data bus. Use Value: Enables deterministic, glitch-free I/O state updates synchronized to system clock, with hardware-initiated reset via PRE lines. |
Use Scenario: Latching upper address bytes during 8085 or Z80 CPU memory access cycles where ALE is unavailable or insufficient. IC Role / Device Role / Timing Role: Functions as an edge-triggered address latch - holds stable address bits while data transfers occur on same bus. Use Value: Provides reliable address hold with 14 ns propagation delay and 30 MHz max clock rate - eliminates timing violations in high-speed memory read/write sequences. |
| Bidirectional Data Bus Interface | Buffered Register File for Control Logic |
Use Scenario: Isolating and controlling direction of data flow between two subsystems sharing a single 8-bit bus (e.g., CPU ↔ peripheral controller). IC Role / Device Role / Timing Role: Serves as dual 4-bit bidirectional bus transceiver - one section for inbound, one for outbound, coordinated via OE and PRE. Use Value: Eliminates need for separate direction-control logic; 3-state outputs prevent bus contention during handshaking transitions. |
Use Scenario: Implementing temporary storage for control word generation in sequencer-based automation systems (e.g., stepper motor controllers). IC Role / Device Role / Timing Role: Operates as a synchronous working register - stores configuration bits (e.g., step mode, acceleration profile) updated under CPU command. Use Value: Preset capability allows instant reinitialization of control state on fault detection, improving system safety and recovery time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4-bit D-register with 3-state outputs applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74ALS874BNT | True (non-inverting) Q outputs; CLR instead of PRE; identical pinout and timing. | Suitable where complemented outputs are not required and active-low clear is preferred over preset. | Select SN74ALS874BNT if system logic expects non-inverted register outputs and uses global clear rather than preset initialization. |
| SN74AS876N | Faster (80 MHz max), higher drive (48 mA sink), AS-family - consumes more power and requires tighter layout for noise control. | Better suited for high-speed data acquisition front-ends where timing margin is critical and power budget allows. | Choose SN74AS876N only when >30 MHz operation is mandatory and thermal/power constraints permit AS-family dissipation. |
Compared with SN74ALS876ANT, SN74ALS874BNT offers functional symmetry with inverted logic polarity, while SN74AS876N trades power efficiency for speed - making SN74ALS876ANT optimal for cost-sensitive, thermally constrained commercial systems requiring reliable 30 MHz bus registration with preset control.
Availability
SN74ALS876ANT is available at Aetrix Electronics and suitable for industrial PLC I/O modules, legacy microprocessor support circuits, and buffered register-based control logic requiring stable component supply and long-term obsolescence management.
Supply support for SN74ALS876ANT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
SN74ALS876ANT belongs to TI's legacy ALS logic product line, engineered for high-reliability, medium-speed digital interfacing in commercial-grade systems where power efficiency and noise immunity outweigh raw speed requirements.
FAQ
What is the function of the PRE pin on the SN74ALS876ANT?
The PRE (preset) pin on the SN74ALS876ANT is an asynchronous active-low input that forces all four Q outputs of its associated register section to logic low immediately - independent of clock state or data inputs. This behavior is confirmed in the function table and logic diagram of the SN74ALS876A datasheet (SDAS061C), where PRE↓ results in Q = L regardless of CLK or D. The SN74ALS876ANT implements this exact function per section.
Does the SN74ALS876ANT support 3.3-V operation?
No, the SN74ALS876ANT does not support 3.3-V operation. Its recommended operating supply voltage is strictly 4.5 V to 5.5 V, with absolute maximum VCC rated at 7 V. Input thresholds (VIH = 2 V min, VIL = 0.8 V max) and output drive characteristics are defined only within the 5-V domain. Using it at 3.3 V will result in undefined logic levels, degraded noise margin, and potential failure to meet timing specifications.
What is the maximum clock frequency supported by the SN74ALS876ANT?
The SN74ALS876ANT supports a maximum clock frequency of 30 MHz under recommended operating conditions (VCC = 4.5 V to 5.5 V, TA = 0°C to 70°C, CL = 50 pF). This value is explicitly stated in the "switching characteristics" table for SN74ALS876A on page 5 of SDAS061C, and is validated by tPLH/tPHL ≤ 14 ns and minimum pulse widths (tw) ≥ 15 ns for CLK high/low.
How does the SN74ALS876ANT differ from the SN74ALS874BNT?
The SN74ALS876ANT differs from SN74ALS874BNT in output polarity and reset functionality: SN74ALS876ANT provides inverting Q outputs and asynchronous PRE inputs, while SN74ALS874BNT provides true Q outputs and asynchronous CLR inputs. Both share identical pinout, timing, and 3-state control. This distinction is clearly documented in the "Choice of True or Inverting Logic" section and function tables of SDAS061C.
Is the SN74ALS876ANT RoHS compliant?
The SN74ALS876ANT (NT package) is not RoHS compliant. Per TI's Packaging Information Addendum, the NT package variant uses leaded solder (SNPB finish) and carries "No" in the RoHS column. RoHS-compliant alternatives exist in SOIC (DW) packages (e.g., SN74ALS876ADWR), but the NT through-hole version remains non-RoHS due to its legacy ceramic/metal construction and leaded finish.
SN74ALS876ANT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74ALS
- Package/Case:
- 24-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Function:
- Master Reset
- Type:
- D-Type
- Output Type:
- Tri-State, Inverted
- Number of Elements:
- 2
- Number of Bits per Element:
- 4
- Clock Frequency:
- 30 MHz
- Max Propagation Delay @ V, Max CL:
- 14ns @ 5V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Current - Quiescent (Iq):
- 21 mA
- Input Capacitance:
- -
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 24-PDIP
SN74ALS876ANT FAQ
1.How can I place an order for SN74ALS876ANT through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74ALS876ANT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74ALS876ANT reliable?
The price and inventory of SN74ALS876ANT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74ALS876ANT is usually 5 days.
3.What payment methods are accepted for SN74ALS876ANT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74ALS876ANT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74ALS876ANT?
SN74ALS876ANT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74ALS876ANT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74ALS876ANT?
For technical support, including SN74ALS876ANT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74ALS876ANT requirements.
6.How does Aetrix verify that SN74ALS876ANT is sourced from the original manufacturer or authorized distributors?
All SN74ALS876ANT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74ALS876ANT meets industry standards.
7.What is the process for return or replacement of SN74ALS876ANT?
All SN74ALS876ANT units undergo pre-shipment inspection (PSI). If there is an issue with SN74ALS876ANT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74ALS876ANT part is unused and in its original packaging.
Return procedure for SN74ALS876ANT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74ALS876ANT Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

