Texas Instruments SN74AUC1G125YEAR
- Part No.:
- SN74AUC1G125YEAR
- Manufacturer:
- Texas Instruments
- Package:
- 5-XFBGA, DSBGA
- Datasheet:
-
SN74AUC1G125YEAR.pdf
- Description:
- IC BUFFER NON-INVERT 2.7V 5DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,446
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74AUC1G125 from Texas Instruments is a single 3-state bus buffer gate optimized for 1.8-V operation, delivering ±8-mA output drive, 2.5-ns max propagation delay at 1.8 V/30 pF, 0.8–2.7-V operating range, and over-voltage tolerant I/Os up to 3.6 V. It serves as a high-speed signal redriver in low-voltage digital interfaces such as memory data paths and FPGA I/O expansion.
For engineers reviewing the SN74AUC1G125 datasheet, SN74AUC1G125 pinout, SN74AUC1G125 application, or SN74AUC1G125 equivalent, key selection criteria include 3-state control timing (tdis/ten), Ioff-enabled partial power-down capability, ULTTL output impedance matching to 50–65-Ω transmission lines, and NanoFree™ DSBGA package compatibility with space-constrained PCB layouts.
Technical Context
The SN74AUC1G125 implements a positive-logic noninverting buffer with active-low 3-state enable (OE), where output Y follows input A when OE is low and enters high-impedance when OE is high. Its ULTTL output structure dynamically adjusts impedance during switching to suppress ringing and support direct drive of short (<15 cm) controlled-impedance lines without external termination.
It features Ioff circuitry that disables outputs and limits back-drive current when VCC = 0 V, enabling safe partial-power-down operation. Input tolerance extends to 3.6 V independent of VCC, allowing interfacing with higher-voltage logic domains while powered from sub-2-V supplies.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 2.7 V - supports ultra-low-voltage SoC I/O rails and mixed-supply domain bridging |
| Max Propagation Delay | 2.5 ns at 1.8 V, 30-pF load - enables reliable operation at >250 MHz clock rates in re-timing paths |
| Output Drive Strength | ±8 mA at 1.8 V - sufficient to drive 50-Ω transmission lines or fan-out to ≥4 LVTTL loads |
| I/O Over-Voltage Tolerance | Up to 3.6 V independent of VCC - eliminates level-shifters when interfacing with 3.3-V peripherals |
| Ioff Current | ±10 µA at 2.7 V - prevents damaging back-current during hot-insertion or partial system power-down |
| Quiescent ICC | 10 µA max - minimizes static power in always-on signal conditioning blocks |
| ESD Rating (HBM) | ±2000 V - meets industrial-grade robustness requirements without external protection |
Pinout & Package
SN74AUC1G125 is available in three 5-pin packages: SOT-23 (DBV, 2.90 mm × 1.60 mm), SC70 (DCK, 2.00 mm × 1.25 mm), and NanoFree™ DSBGA (YZP, 1.39 mm × 0.89 mm). All variants share identical pin functionality and logic behavior.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (OE) | Active-low output enable input | Drives Y to high-impedance when high; must be pulled up to VCC during power sequencing to avoid bus contention |
| 2 (A) | Noninverting logic input | Accepts 0.8–3.6-V signals; requires termination to VCC or GND if unused to prevent floating inputs |
| 3 (GND) | Ground reference | Primary return path for output current and internal logic; must be low-inductance connection for signal integrity |
| 4 (Y) | 3-state noninverting output | Drives A when OE = low; presents >10⁹ Ω impedance when OE = high; supports bidirectional bus arbitration |
| 5 (VCC) | Positive supply | Supplies core logic and output drivers; requires local 0.1-µF bypass capacitor placed adjacent to pin |
Key Features
| Feature | Design Value |
|---|---|
| ULTTL Output Architecture | Dynamic impedance control enables clean edge transitions into 50–65-Ω lines without external series resistors or terminations |
| Ioff Partial Power-Down | Prevents back-current flow when VCC = 0 V, supporting hot-swap and multi-rail power sequencing in modular systems |
| NanoFree™ DSBGA Packaging | Die-as-package construction reduces footprint to 1.39 mm × 0.89 mm and eliminates bond wire inductance for RF-sensitive applications |
| Over-Voltage Tolerant I/Os | 3.6-V input/output tolerance at any VCC from 0.8 V to 2.7 V - simplifies voltage-domain bridging in heterogeneous SoC designs |
| Low-Power Operation | 10-µA max ICC and 2-pF typical input capacitance minimize dynamic and static power in battery-powered edge nodes |
Applications
| Memory Interface Signal Redriving | FPGA I/O Expansion Buffering |
|---|---|
Use Scenario: Re-timing and strengthening DDRx data strobes or address/command lines between memory controller and LPDDR chip. IC Role / Device Role / Timing Role: Single-line 3-state buffer providing clean, low-skew signal regeneration with programmable enable control. Use Value: Enables reliable 1.8-V signaling across 8–12 cm PCB traces without added termination, reducing BOM count and layout complexity. |
Use Scenario: Isolating and driving configurable I/O banks on Xilinx Artix or Intel Cyclone FPGAs to external sensors or displays. IC Role / Device Role / Timing Role: Direction-controlled bus buffer managing shared data lines between FPGA and peripheral ICs. Use Value: Ioff protection prevents damage during FPGA configuration phase when VCC may be unpowered while peripherals remain live. |
| Low-Power Sensor Hub Signal Conditioning | USB-C Sideband Use (SBU) Line Control |
Use Scenario: Level-shifting and buffering I²C/SPI signals from 1.8-V MEMS sensors to 3.3-V microcontroller in wearable devices. IC Role / Device Role / Timing Role: Voltage-tolerant buffer enabling bidirectional communication across supply domains with no external level shifters. Use Value: 3.6-V I/O tolerance allows direct connection to 3.3-V MCU pins while powered from 1.8-V rail, cutting component count by one per channel. |
Use Scenario: Enabling/disabling auxiliary analog signals (e.g., DisplayPort AUX CH, audio) on USB-C connectors via host-controlled OE. IC Role / Device Role / Timing Role: Low-capacitance 3-state switch routing analog sideband signals only when actively required. Use Value: <10-µA quiescent current and <2.5-ns enable/disable timing meet USB-C specification requirements for fast, low-power sideband control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DBVR | Wider VCC range (1.65–5.5 V); lower drive (±24 mA @ 3.3 V); slower tpd (3.7 ns @ 3.3 V/30 pF) | Better suited for 3.3-V legacy systems; lacks 0.8-V operation and 3.6-V I/O tolerance | Select when interoperability with 5-V tolerant systems is required and 1.8-V optimization is not critical |
| NC7SZ125P5X | Smaller SC70-5 footprint (2.0 × 1.25 mm); same 1.65–3.6-V range; higher ICC (30 µA max); no Ioff | Lacks partial-power-down capability; less robust for hot-swap scenarios | Choose for cost-sensitive, space-constrained designs where Ioff and sub-1-V operation are unnecessary |
Compared with SN74LVC1G125DBVR and NC7SZ125P5X, the SN74AUC1G125 uniquely delivers sub-1-V operation, 3.6-V I/O tolerance, and Ioff in a NanoFree™ package-making it the only option for next-gen ultra-low-power, mixed-voltage, and hot-pluggable interface designs.
Availability
SN74AUC1G125 is available at Aetrix Electronics and suitable for memory interface signal redriving, FPGA I/O expansion buffering, low-power sensor hub signal conditioning, and USB-C sideband use (SBU) line control requiring stable component supply across automotive infotainment, industrial IoT gateways, and portable medical devices.
Supply support for SN74AUC1G125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in precision electronics and industrial-grade reliability.
The SN74AUC1G125 belongs to TI's AUC "sub-1-V Little Logic" family, engineered specifically for speed and signal integrity in ultra-low-voltage digital interfaces-targeting applications where 1.8-V operation, minimal propagation delay, and transmission-line compatibility are critical.
FAQ
What is the minimum supply voltage supported by the SN74AUC1G125?
The SN74AUC1G125 operates down to 0.8 V, enabling integration into ultra-low-power domains such as battery-backed real-time clocks, energy-harvesting sensor nodes, and deep-sleep MCU subsystems. This 0.8-V minimum is confirmed in Section 6.3 (Recommended Operating Conditions) of the official TI datasheet SCES382M.
Does the SN74AUC1G125 support hot-swap or partial power-down operation?
Yes, the SN74AUC1G125 includes Ioff circuitry that disables all outputs and limits leakage to ±10 µA when VCC = 0 V, preventing back-current flow during hot-insertion or staged power sequencing. This feature is explicitly documented in Section 8.3.3 and Table 6.5 of the SN74AUC1G125 datasheet.
Can the SN74AUC1G125 drive a 50-Ω transmission line directly?
Yes-the SN74AUC1G125's ULTTL output structure is optimized for direct connection to 50–65-Ω controlled-impedance lines up to 15 cm long, eliminating need for external series resistors or parallel terminations. This capability is validated in Figure 9-2 and Section 8.3.1 of the TI datasheet.
What is the maximum propagation delay of the SN74AUC1G125 at 1.8 V?
The maximum propagation delay (tpd) of the SN74AUC1G125 is 2.5 ns under conditions of VCC = 1.8 V ± 0.15 V and CL = 30 pF, as specified in Table 6.7 of the official datasheet. This value ensures reliable operation in high-speed digital paths up to 250 MHz.
Which packages are available for the SN74AUC1G125?
The SN74AUC1G125 is offered in three industry-standard 5-pin packages: SOT-23 (DBV), SC70 (DCK), and NanoFree™ DSBGA (YZP). Package dimensions and mechanical drawings are detailed in Section 13 and the Package Option Addendum of the TI datasheet SCES382M.
SN74AUC1G125YEAR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUC
- Package/Case:
- 5-XFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 9mA, 9mA
- Voltage - Supply:
- 0.8V ~ 2.7V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-DSBGA (1.4x0.9)
SN74AUC1G125YEAR FAQ
1.How can I place an order for SN74AUC1G125YEAR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUC1G125YEAR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUC1G125YEAR reliable?
The price and inventory of SN74AUC1G125YEAR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUC1G125YEAR is usually 5 days.
3.What payment methods are accepted for SN74AUC1G125YEAR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74AUC1G125YEAR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74AUC1G125YEAR?
SN74AUC1G125YEAR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AUC1G125YEAR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUC1G125YEAR?
For technical support, including SN74AUC1G125YEAR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUC1G125YEAR requirements.
6.How does Aetrix verify that SN74AUC1G125YEAR is sourced from the original manufacturer or authorized distributors?
All SN74AUC1G125YEAR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUC1G125YEAR meets industry standards.
7.What is the process for return or replacement of SN74AUC1G125YEAR?
All SN74AUC1G125YEAR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUC1G125YEAR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUC1G125YEAR part is unused and in its original packaging.
Return procedure for SN74AUC1G125YEAR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74AUC1G125YEAR Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

