Texas Instruments SN74AUC2G126YZPR
- Part No.:
- SN74AUC2G126YZPR
- Manufacturer:
- Texas Instruments
- Package:
- 8-XFBGA, DSBGA
- Datasheet:
-
SN74AUC2G126YZPR.pdf
- Description:
- IC BUFFER NON-INVERT 2.7V 8DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:3,497
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Product details
Overview
SN74AUC2G126YZPR from Texas Instruments is a dual 3-state bus buffer gate optimized for 1.65–1.95 V operation, delivering ±8 mA output drive at 1.8 V, sub-1.9 ns propagation delay, and 10 µA ICC quiescent current. It serves as a level-shifting, bidirectional bus interface in ultra-low-voltage portable logic systems.
For engineers reviewing the SN74AUC2G126YZPR datasheet, SN74AUC2G126YZPR pinout, SN74AUC2G126YZPR application, or SN74AUC2G126YZPR equivalent, key selection criteria include Ioff-enabled partial-power-down support, 3.6-V I/O tolerance for mixed-mode interfacing, NanoFree™ WCSP package footprint, and guaranteed 1.8-V timing performance.
Technical Context
This device implements two independent noninverting buffers, each with an active-high output-enable (OE) control enabling high-impedance state. Its AUC logic family ensures sub-1-V operability down to 0.8 V while maintaining full 3.6-V I/O tolerance - critical for voltage-domain bridging between 1.2-V/1.8-V cores and legacy 3.3-V peripherals.
The integrated Ioff circuitry disables outputs during power-down, blocking reverse current flow; latch-up immunity exceeds 100 mA per JESD 78 Class II. ESD protection meets 2000-V HBM, 200-V MM, and 1000-V CDM standards - essential for handheld and battery-powered assembly environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 2.7 V - supports sub-1-V operation and mixed-voltage system integration |
| tpd (1.8 V, CL = 15 pF) | 1.9 ns max - enables high-speed data routing in compact portable logic paths |
| Output Drive (1.8 V) | ±8 mA - sufficient to drive 15-pF loads across PCB traces without external buffering |
| Ioff Current | ±10 µA max - prevents backflow damage when VCC = 0 while I/O pins remain biased |
| IOZ (High-Z Leakage) | ±10 µA max - maintains signal integrity on shared buses during disable states |
| ESD Rating (HBM) | 2000 V - meets industrial handling requirements without additional protection circuitry |
| Power Consumption (ICC) | 10 µA typical at 1.8 V - extends battery life in always-on sensor interface modules |
Pinout & Package
NanoFree™ WCSP (YZP) package: 0.23-mm large bump, 8-terminal DSBGA, bottom-side solder bumps, pin 1 identified by solder-bump composition marker (• = Pb-free). Dimensions: 1.35 mm × 0.95 mm × 0.44 mm (max height).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCC | Main supply input - must be decoupled locally; powers both buffers and OE logic |
| 2 | 1A | Input of Buffer 1 - accepts 0.8–3.6 V signals; compatible with 1.2-V, 1.8-V, and 3.3-V logic |
| 3 | 1Y | Output of Buffer 1 - 3-state capable; driven high/low or high-Z based on 1OE |
| 4 | GND | Ground reference - requires low-inductance connection to minimize switching noise |
| 5 | 2A | Input of Buffer 2 - electrically isolated from Buffer 1; supports independent signal routing |
| 6 | 2Y | Output of Buffer 2 - identical drive and timing specs to 1Y; shares no internal path with 1Y |
| 7 | 2OE | Active-high enable for Buffer 2 - tied low to disable; pulldown resistor recommended for power sequencing |
| 8 | 1OE | Active-high enable for Buffer 1 - controls 1Y only; OE inputs are not internally tied |
Key Features
| Feature | Design Value |
|---|---|
| NanoFree™ WCSP packaging | Die-as-package construction reduces board area by >70% vs. SSOP/DCT - ideal for space-constrained wearables and IoT sensors |
| Ioff partial-power-down support | Enables hot-plug and dynamic power gating without risk of back-current - required for USB-C accessory detection and battery fuel gauging |
| 3.6-V I/O tolerance | Allows direct connection to 3.3-V GPIOs while powered from 1.8-V rail - eliminates level translators in mixed-voltage SoC interfaces |
| Sub-1.9 ns tpd at 1.8 V | Meets timing closure for 500+ MHz data bursts in memory-mapped peripheral bridges and FPGA configuration links |
| 10 µA ICC at 1.8 V | Reduces standby power in always-listening voice trigger circuits - critical for multi-week battery life in hearables |
Applications
| Mobile Sensor Hub Interface | Low-Power Wearable Display Driver |
|---|---|
|
Use Scenario: Interfacing MEMS accelerometers (1.2-V I²C) and barometers (1.8-V SPI) to an application processor running at 1.8-V core voltage. IC Role / Device Role / Timing Role: Dual-directional voltage-level translation and bus isolation between heterogeneous sensor domains. Use Value: Eliminates discrete level shifters and saves 1.2 mm² PCB area via YZP package - directly enabling <10-mm-diameter earbud form factors. |
Use Scenario: Driving segmented OLED display lines from a microcontroller with limited GPIO drive strength and variable supply voltage (1.2–1.8 V). IC Role / Device Role / Timing Role: Output buffer with 3-state capability to multiplex display segments and reduce capacitive loading on MCU pins. Use Value: ±8-mA drive sustains 100-kHz update rates under 15-pF load; Ioff prevents display ghosting during MCU sleep modes. |
| USB-C Accessory Detection Logic | Industrial Battery Fuel Gauge Interface |
|
Use Scenario: Detecting CC line voltage levels and enabling/disabling pull-up resistors during USB-C plug insertion and orientation negotiation. IC Role / Device Role / Timing Role: Fast-response, low-leakage switch controlling bias networks on CC1/CC2 lines. Use Value: 1.9-ns tpd ensures real-time response to CC transients; 3.6-V I/O tolerance handles up to 5.5-V fault conditions safely. |
Use Scenario: Isolating SMBus communication between a fuel gauge IC (3.3-V tolerant) and a 1.8-V microcontroller in smart battery packs. IC Role / Device Role / Timing Role: Bidirectional bus buffer with independent OE control for clock/data lines and fault signaling. Use Value: Ioff blocks reverse current during pack removal; ±10-µA IOZ leakage preserves SMBus signal integrity over 10-year shelf life. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AUC2G125YZPR | Inverting logic function (A → Y̅), same speed, drive, and package | Required where signal polarity inversion is needed in bus arbitration or enable logic | Select only if functional inversion aligns with system-level timing and control architecture |
| SN74LVC2G126DCUR | VSSOP-8 (DCU) package, 1.65–5.5 V VCC range, 3.5 ns tpd at 3.3 V | Better suited for 3.3-V dominant systems; larger footprint but higher voltage margin | Choose when board layout allows 2.3-mm × 2.0-mm DCU package and 3.3-V compatibility is prioritized over size |
Compared with SN74AUC2G126YZPR, SN74AUC2G125YZPR provides identical electrical performance but inverted logic - requiring redesign of downstream enable paths; SN74LVC2G126DCUR trades NanoFree™ area savings for broader voltage range and mature VSSOP manufacturability - suitable for cost-sensitive, non-size-constrained industrial designs.
Availability
SN74AUC2G126YZPR is available at Aetrix Electronics and suitable for mobile sensor hubs, wearable display interfaces, USB-C accessory detection circuits, industrial battery fuel gauge links, and ultra-low-power IoT edge nodes requiring stable component supply across extended production lifecycles.
Supply support for SN74AUC2G126YZPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in low-power logic innovation.
The SN74AUC2G126YZPR belongs to TI's AUC Sub-1-V Little Logic family - engineered specifically for space- and power-constrained portable electronics requiring robust mixed-signal interfacing without voltage translation overhead.
FAQ
What is the maximum operating temperature range for SN74AUC2G126YZPR?
The SN74AUC2G126YZPR is fully specified for operation from –40°C to +85°C ambient temperature. This range is validated across all electrical parameters including tpd, VOH/VOL, and Ioff, making it suitable for consumer wearables and industrial edge sensors exposed to thermal cycling.
Does SN74AUC2G126YZPR support true bidirectional data flow?
No - SN74AUC2G126YZPR is a unidirectional buffer: signal flows from A to Y only. For bidirectional bus applications, two SN74AUC2G126YZPR devices must be used in opposing directions with coordinated OE control, or a dedicated transceiver like SN74AVC2T245 should be selected.
Can SN74AUC2G126YZPR be used with a 3.3-V microcontroller I/O pin while powered from 1.8 V?
Yes - SN74AUC2G126YZPR features 3.6-V I/O tolerance, so its inputs and outputs safely accept and drive 3.3-V signals even when VCC = 1.8 V. This eliminates external level shifters in mixed-voltage SoC-to-peripheral interfaces.
What is the recommended pull-down resistance for OE pins on SN74AUC2G126YZPR?
Texas Instruments recommends a pulldown resistor ≤10 kΩ on each OE pin to ensure reliable high-impedance state during power-up. This value balances leakage current (≤1 µA) against noise immunity and rise time - verified in TI application report SCEA027.
Is the NanoFree™ YZP package of SN74AUC2G126YZPR compatible with standard reflow profiles?
Yes - SN74AUC2G126YZPR's YZP package is rated MSL Level-1 with unlimited floor life and peak reflow tolerance up to 260°C. Its Pb-free solder bumps and thermal impedance (θJA = 102°C/W) support standard lead-free reflow processes without special profiling.
SN74AUC2G126YZPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUC
- Package/Case:
- 8-XFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 9mA, 9mA
- Voltage - Supply:
- 0.8V ~ 2.7V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DSBGA
SN74AUC2G126YZPR FAQ
1.How can I place an order for SN74AUC2G126YZPR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUC2G126YZPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of SN74AUC2G126YZPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUC2G126YZPR is usually 5 days.
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For technical support, including SN74AUC2G126YZPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUC2G126YZPR requirements.
6.How does Aetrix verify that SN74AUC2G126YZPR is sourced from the original manufacturer or authorized distributors?
All SN74AUC2G126YZPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUC2G126YZPR meets industry standards.
7.What is the process for return or replacement of SN74AUC2G126YZPR?
All SN74AUC2G126YZPR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUC2G126YZPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUC2G126YZPR part is unused and in its original packaging.
Return procedure for SN74AUC2G126YZPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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