Texas Instruments SN74AUP1G126DRLR

Overview

SN74AUP1G126DRLR from Texas Instruments is a single low-power bus buffer gate with tri-state output, designed for point-to-point signal routing in battery-powered portable systems. It operates across 0.8 V to 3.6 V supply, delivers 4.6 ns max propagation delay at 3.3 V, consumes ≤0.9 µA static current, and supports Ioff partial-power-down mode for system-level power sequencing - used in SSDs, tablets, and wireless peripherals.

For engineers reviewing the SN74AUP1G126DRLR datasheet, SN74AUP1G126DRLR pinout, SN74AUP1G126DRLR application, or SN74AUP1G126DRLR equivalent, key selection criteria include its ultra-low ICC (0.9 µA max), 3.6-V I/O tolerance for mixed-voltage interfacing, input-disable capability for floating inputs, and SOT-5X3 package (1.60 mm × 1.20 mm) optimized for space-constrained PCB layouts.

Technical Context

This device implements a non-inverting buffer (Y = A) with active-high output enable (OE), enabling precise control of signal flow on shared buses or interconnect lines. Its balanced CMOS push-pull output drives both high and low states symmetrically, supporting clean edge transitions into light capacitive loads up to 30 pF.

The AUP family architecture integrates input hysteresis for noise immunity against slow input transitions, clamp diodes for ESD robustness (2000-V HBM), and Ioff circuitry that isolates inputs/outputs during power-down - preventing back-current damage when VCC = 0 V while maintaining ≤0.6 µA leakage over –40°C to +85°C.

Key Specifications

Pinout & Package

SOT-5X3 (5-pin) package: ultra-compact 1.60 mm × 1.20 mm footprint with 0.5-mm pitch, using TI's NanoStar™ die-as-package technology for minimal board area and thermal resistance (RθJA = 295.1°C/W).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus buffer applications.

Compared with SN74LVC1G126DBVR and NC7SZ126P5X, SN74AUP1G126DRLR uniquely combines sub-µA static power, 0.8-V minimum operation, Ioff isolation, and input hysteresis - making it the only option for battery-critical, multi-rail, and thermally constrained portable designs.

Availability

SN74AUP1G126DRLR is available at Aetrix Electronics and suitable for audio docks, SSDs, tablets, and wireless peripherals requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SN74AUP1G126DRLR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with core expertise in low-power logic, precision analog, and high-reliability automotive ICs.

The AUP family - including SN74AUP1G126DRLR - was engineered specifically for ultra-low-power portable electronics, targeting extended battery life, mixed-voltage interoperability, and robust operation in thermally constrained handheld and wearable devices.

FAQ

What is the maximum propagation delay of SN74AUP1G126DRLR at 3.3 V?

The maximum propagation delay (tpd) of SN74AUP1G126DRLR is 4.6 ns at VCC = 3.3 V ± 0.3 V, CL = 5 pF, and TA = –40°C to +85°C - measured from A to Y under worst-case process/voltage/temperature conditions per TI SCES596G.

Does SN74AUP1G126DRLR support partial-power-down operation?

Yes, SN74AUP1G126DRLR fully supports partial-power-down via its Ioff feature: when VCC = 0 V, all I/Os enter high-impedance state with ≤0.6 µA leakage over –40°C to +85°C, preventing back-current damage during hot-swap or staged power sequencing.

What package type is used for SN74AUP1G126DRLR?

SN74AUP1G126DRLR uses the SOT-5X3 (5-pin) package - a 1.60 mm × 1.20 mm NanoStar™ package where the silicon die serves as the mechanical substrate, minimizing footprint and thermal resistance (RθJA = 295.1°C/W).

Can SN74AUP1G126DRLR accept input voltages higher than its supply voltage?

Yes, SN74AUP1G126DRLR features overvoltage-tolerant inputs rated up to 4.6 V absolute maximum - allowing 3.3-V signals to be safely applied even when VCC = 1.2 V, enabling mixed-voltage interfacing without external level shifters.

How should the OE pin be handled during power-up to ensure tri-state default?

To guarantee high-impedance output at power-up/power-down, OE must be tied to GND through a pulldown resistor; TI specifies minimum resistance based on driver sink capability - typically 10 kΩ suffices for most MCU-driven implementations of SN74AUP1G126DRLR.