Texas Instruments SN74AUP1G58YZTR

Overview

SN74AUP1G58YZTR from Texas Instruments is a low-power configurable multiple-function logic gate in a 6-pin YZP (NanoStar™ DSBGA) package. It implements AND, OR, NAND, NOR, XNOR, inverter, or noninverter functions via three input pins (In0–In2), features Schmitt-trigger inputs for noise immunity, operates from 0.8 V to 3.6 V, and delivers 5.5 ns max propagation delay at 3.3 V - ideal for battery-powered portable interface logic.

For engineers reviewing the SN74AUP1G58YZTR datasheet, SN74AUP1G58YZTR pinout, SN74AUP1G58YZTR application, or SN74AUP1G58YZTR equivalent, key selection criteria include its ultra-low ICC (0.9 mA max), Ioff support for partial-power-down mode, 3.6-V I/O tolerance, 1.5 pF typical input capacitance, and configurable function mapping across VCC = 0.8–3.6 V.

Technical Context

The SN74AUP1G58YZTR uses a 3-bit input configuration (In0, In1, In2) to select one of eight logic functions via truth table lookup, enabling flexible gate-level reconfiguration without external programming. Its Schmitt-trigger inputs provide hysteresis (ΔVT up to 1.31 V at 3 V), supporting slow-rising signals and robust noise rejection in noisy environments.

It integrates Ioff circuitry that disables outputs during power-down, preventing backflow current when VCC = 0 V, and maintains 3.6-V I/O tolerance across the full 0.8–3.6 V supply range - enabling mixed-voltage signal interfacing between legacy and low-voltage subsystems.

Key Specifications

Pinout & Package

Packaged in a 6-ball NanoStar™ DSBGA (YZP) with 0.5 mm max height, 0.225 mm ball pitch, and A1 corner ball marking. Ball layout follows JEDEC MO-293 variant UAAD with exposed die as package body.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G58DBVR and SN74AUP2G00DCUR, the SN74AUP1G58YZTR uniquely combines 3-bit configurability, Schmitt-trigger inputs, Ioff, and sub-1 V operation - making it the only option for compact, ultra-low-power, noise-immune, mixed-voltage reconfigurable logic in space-constrained portable designs.

Availability

SN74AUP1G58YZTR is available at Aetrix Electronics and suitable for wearable electronics, battery-powered IoT sensors, and USB-C PD controllers requiring stable component supply, long-term lifecycle support, and RoHS-compliant NanoStar™ packaging.

Supply support for SN74AUP1G58YZTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with broad industrial, automotive, and consumer design expertise.

The AUP family targets ultra-low-power portable applications, delivering optimized static/dynamic power consumption across 0.8–3.6 V while maintaining signal integrity - directly addressing battery life and EMI challenges in wearables and handheld devices.

FAQ

What logic functions does the SN74AUP1G58YZTR support?

The SN74AUP1G58YZTR supports eight logic functions determined by its three inputs (In0–In2): AND, OR, NAND, NOR, XNOR, inverter, noninverter, and one additional pattern per truth table. Each combination maps directly to a defined output state - no internal registers or configuration registers are involved; function selection is purely combinational and immediate.

Does the SN74AUP1G58YZTR require external pull-up or pull-down resistors on unused inputs?

Yes - all unused inputs of the SN74AUP1G58YZTR must be held at VCC or GND to ensure proper device operation and avoid floating-node instability. TI explicitly recommends this in SCBA004; leaving inputs unconnected may cause excessive ICC, unpredictable output states, or increased susceptibility to ESD-induced latch-up.

Can the SN74AUP1G58YZTR operate at 1.2 V supply voltage?

Yes - the SN74AUP1G58YZTR is fully specified for operation from 0.8 V to 3.6 V, including 1.2 V. At 1.2 V, it delivers tpd ≤ 13.8 ns (CL = 5 pF), ICC ≤ 0.9 mA, and maintains Schmitt-trigger hysteresis (VT+ = 0.53 V, VT− = 0.26 V), making it suitable for energy-harvesting and sub-1.8 V microcontroller interfaces.

Is the SN74AUP1G58YZTR pin-compatible with other AUP-series single-gate devices?

No - the SN74AUP1G58YZTR uses a unique 3-input + output + VCC + GND pinout (In0, In1, In2, Y, VCC, GND) that differs from standard 5-pin AUP gates (e.g., SN74AUP1G00). Its YZP package has a 6-ball DSBGA layout incompatible with SOT-23 or SC-70 footprints - PCB redesign is required for substitution.

What is the maximum capacitive load the SN74AUP1G58YZTR can drive reliably?

The SN74AUP1G58YZTR is characterized up to CL = 30 pF in datasheet switching specs. At 3.3 V, tpd remains ≤ 7.3 ns (max) with CL = 30 pF. Driving loads beyond 30 pF may increase propagation delay nonlinearly and risk signal integrity degradation - for >30 pF, verify timing margins with actual board parasitics and consider buffering.