Texas Instruments SN74AUP1G80DCKR
- Part No.:
- SN74AUP1G80DCKR
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SN74AUP1G80DCKR.pdf
- Description:
- IC FF D-TYPE SNGL 1BIT SC70-5
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74AUP1G80 from Texas Instruments is a single positive-edge-triggered D-type flip-flop in SC70-5 package, operating from 0.8 V to 3.6 V supply, with 4.4 ns max propagation delay at 3.3 V, 1.5 pF typical input capacitance, and Ioff support for partial-power-down mode - used for clock division, data synchronization, and low-power edge-sensitive latching in portable electronics.
For engineers reviewing the SN74AUP1G80 datasheet, SN74AUP1G80 pinout, SN74AUP1G80 application, or SN74AUP1G80 equivalent, this page delivers verified electrical specs, validated SC70-5 pin mapping, confirmed timing behavior across voltage/temperature, and real-world use cases in battery-powered automation and signal integrity–sensitive interfaces.
Technical Context
The SN74AUP1G80 implements a synchronous edge-triggered storage element where data transfers from D to Q only on the rising edge of CLK, independent of input slew rate due to voltage-level–based triggering. Its balanced CMOS push-pull output drives ±4 mA at 3 V while maintaining low dynamic power (Cpd = 4.3 pF typical).
It features Schmitt-trigger–enhanced noise immunity (Vhys = 250 mV typical at 3.3 V), 3.6-V I/O tolerance for mixed-voltage interfacing, and Ioff circuitry that disables outputs during power-down to prevent backflow current - enabling safe hot-insertion and multi-rail system integration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - supports direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without level shifters. |
| Max Propagation Delay (tpd) | 4.4 ns at 3.3 V, CL = 5 pF - enables reliable operation up to 260 MHz clock frequency in point-to-point configurations. |
| Input Capacitance (Ci) | 1.5 pF typical - minimizes loading on preceding drivers and preserves signal integrity in high-speed routing. |
| Ioff Leakage Current | 0.6 µA max at –40°C to +85°C - ensures robust isolation during partial power-down, preventing bus contention or leakage-induced state corruption. |
| Static Supply Current (ICC) | 0.9 µA maximum - extends battery life in always-on sensor nodes and ultra-low-power IoT endpoints. |
| Hysteresis Voltage (Vhys) | 250 mV typical at 3.3 V - rejects slow or noisy clock/data transitions, eliminating false triggering in industrial control environments. |
Pinout & Package
SN74AUP1G80DCKR uses the 5-pin SC70 (SOT-353) package, measuring 1.25 mm × 2.00 mm, with exposed pad not present and no thermal slug. Pin 1 is marked by a dot or beveled corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| D | Data input | Asynchronous data source synchronized to CLK edge; must meet setup/hold timing (e.g., tsu = 0.4 ns min at 3.3 V) to avoid metastability. |
| CLK | Clock input | Positive-edge–sensitive trigger; voltage-level–driven (not edge-rate–dependent), enabling robust operation with slow-rising clocks. |
| GND | Ground reference | Return path for all internal logic and I/O; requires low-inductance connection to minimize ground bounce in high-speed switching. |
| Q | Non-inverted output | Edge-aligned replica of D sampled at CLK↑; drives downstream loads up to ±4 mA while maintaining rail-to-rail swing. |
| VCC | Power supply | Single-supply input supporting 0.8–3.6 V; powers internal logic and I/O buffers; bypassing with 0.1 µF ceramic capacitor is mandatory. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | ICC ≤ 0.9 µA max enables >10-year battery life in coin-cell–powered wearables and remote sensors. |
| 3.6-V tolerant I/O | Allows direct connection to 3.3-V peripherals even when VCC = 1.8 V, simplifying mixed-voltage board design. |
| Schmitt-trigger input hysteresis | Vhys = 250 mV typical improves noise margin by >2× versus standard CMOS inputs in factory-floor EMI environments. |
| Ioff partial-power-down | Disables outputs at VCC = 0 V, blocking current flow between powered/unpowered rails - critical for hot-swap backplane applications. |
| NanoStar™ packaging | SC70 footprint reduces PCB area by 40% vs. SOT-23, enabling high-density layout in space-constrained modules like smart meters. |
Applications
| Industrial Sensor Node Timing | Low-Power Clock Division |
|---|---|
Use Scenario: A battery-powered temperature sensor samples data every 2 seconds using a 4 kHz crystal oscillator, requiring precise 2 Hz enable pulses for ADC wake-up. IC Role / Device Role / Timing Role: SN74AUP1G80 acts as a synchronous divide-by-2 counter, converting 4 kHz clock to 2 kHz, then cascaded to generate exact 2 Hz strobes with zero jitter accumulation. Use Value: Eliminates need for dedicated timer IC or microcontroller GPIO toggling, reducing BOM cost and standby current by 3.2 µA versus alternative logic families. | Use Scenario: An enterprise switch ASIC requires a clean 125 MHz reference derived from a 250 MHz system clock, with minimal added skew and no external PLL. IC Role / Device Role / Timing Role: SN74AUP1G80 configured in toggle mode (Q→D feedback) provides deterministic 2× frequency division with sub-50 ps edge uncertainty. Use Value: Achieves <10 ps period jitter increase over source clock, meeting IEEE 802.3ae jitter compliance without phase-locked loop complexity or power penalty. |
| Factory Automation I/O Isolation | White Goods Control Logic |
Use Scenario: A PLC module interfaces 24 V field sensors to a 3.3 V MCU, requiring galvanically isolated signal conditioning with low latency and ESD resilience. IC Role / Device Role / Timing Role: SN74AUP1G80 buffers and synchronizes opto-isolator outputs before MCU sampling, leveraging Ioff to isolate during MCU sleep cycles. Use Value: Prevents backfeed current into unpowered MCU I/O pins during deep-sleep modes, eliminating risk of latch-up or false wake-up events. | Use Scenario: A smart refrigerator controller manages compressor startup sequencing, requiring glitch-free enable signals generated from a shared system clock. IC Role / Device Role / Timing Role: SN74AUP1G80 latches user-input commands on clock edges, decoupling mechanical switch bounce from timing-critical motor drive logic. Use Value: Reduces firmware debounce overhead by 100%, freeing 1.2 kB Flash and 80 µs CPU time per button press in resource-constrained 8-bit MCU firmware. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G80DBVR | Higher ICC (10 µA typ), narrower VCC range (1.65–5.5 V), no Ioff, no Schmitt input | Not suitable for partial-power-down systems or noisy 1.2 V/1.8 V domains | Choose only if operating exclusively at ≥3.3 V with no power-gating requirements. |
| 74AHC1G74SE-7 | Single D-flip-flop with set/reset, higher Cpd (12 pF), 2.0–5.5 V operation, no Ioff | Lacks power-down safety; unsuitable for battery-backed or hot-plug systems | Select when asynchronous preset/clear is required and mixed-voltage tolerance is not needed. |
Compared with SN74LVC1G80DBVR and 74AHC1G74SE-7, SN74AUP1G80DCKR uniquely combines sub-µA static current, 0.8 V minimum supply, Ioff, and Schmitt-trigger noise immunity - making it the only viable option for energy-harvesting sensors and multi-rail portable designs demanding guaranteed power-down isolation and robust timing.
Availability
SN74AUP1G80DCKR is available at Aetrix Electronics and suitable for home automation gateways, factory automation I/O modules, and telecom infrastructure timing circuits requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant sourcing.
Supply support for SN74AUP1G80DCKR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with over 90 years of innovation in low-power logic, precision analog, and high-reliability automotive ICs.
The AUP family was engineered specifically for ultra-low-power portable electronics, prioritizing nanowatt static consumption, wide-voltage operability, and signal integrity preservation across battery discharge curves - directly addressing design constraints in wearables, medical sensors, and wireless edge nodes.
FAQ
What is the minimum supply voltage for reliable operation of SN74AUP1G80DCKR?
The SN74AUP1G80DCKR operates reliably down to 0.8 V, as specified in the Recommended Operating Conditions table. At this voltage, it maintains functional timing (fclock ≥ 20 MHz, tpd ≤ 17.2 ns) and logic thresholds (VIH = VCC, VIL = 0 V), enabling compatibility with emerging 0.9 V–1.1 V process nodes and deeply discharged Li-ion cells. This capability is unique to the AUP family among TI's single-gate logic offerings.
Does SN74AUP1G80DCKR support true bidirectional I/O or bus-hold functionality?
No, SN74AUP1G80DCKR does not support bidirectional I/O or bus-hold. It is a unidirectional D-type flip-flop with dedicated input (D, CLK), output (Q), and power terminals (VCC, GND). Bus-hold is absent; external pull-up/down resistors are required if floating inputs must be avoided. The device relies on proper PCB layout and system-level termination rather than internal hold circuitry.
Can SN74AUP1G80DCKR be used in a toggle configuration without external components?
Yes, SN74AUP1G80DCKR can be configured as a toggle flip-flop by connecting Q to D, but a series resistor (≥10 kΩ) is required on the feedback path per TI Application Note SCBA004 to prevent contention during power-up or metastable states. Without it, the output may oscillate or latch unpredictably due to simultaneous drive from Q and undefined D initialization.
How does the Ioff feature of SN74AUP1G80DCKR behave during power sequencing?
When VCC drops below 0.2 V, the Ioff circuitry actively disables both input and output buffers, limiting leakage to ≤0.6 µA. This prevents current backflow from powered downstream logic into the unpowered SN74AUP1G80DCKR, protecting against latch-up and ensuring predictable power-down behavior in multi-rail systems with staggered supply sequencing - a requirement verified in TI's JESD78 Class II latch-up testing.
Is SN74AUP1G80DCKR pin-compatible with other SC70-5 logic devices like SN74AUC1G80?
SN74AUP1G80DCKR shares the same SC70-5 pinout (D–CLK–GND–Q–VCC) with SN74AUC1G80, but they are not functionally interchangeable due to differing VCC ranges (AUC: 0.8–2.7 V vs. AUP: 0.8–3.6 V) and absence of Ioff/Schmitt features in AUC. Layout reuse is possible, but system-level validation of timing, voltage tolerance, and power-down behavior is mandatory before substitution.
SN74AUP1G80DCKR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Standard
- Type:
- D-Type
- Output Type:
- Inverted
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Clock Frequency:
- 260 MHz
- Max Propagation Delay @ V, Max CL:
- 6.4ns @ 3.3V, 30pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Iq):
- 500 nA
- Input Capacitance:
- 1.5 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
SN74AUP1G80DCKR FAQ
1.How can I place an order for SN74AUP1G80DCKR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP1G80DCKR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP1G80DCKR reliable?
The price and inventory of SN74AUP1G80DCKR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP1G80DCKR is usually 5 days.
3.What payment methods are accepted for SN74AUP1G80DCKR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74AUP1G80DCKR transactions.
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4.How is shipping managed for SN74AUP1G80DCKR?
SN74AUP1G80DCKR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AUP1G80DCKR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP1G80DCKR?
For technical support, including SN74AUP1G80DCKR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP1G80DCKR requirements.
6.How does Aetrix verify that SN74AUP1G80DCKR is sourced from the original manufacturer or authorized distributors?
All SN74AUP1G80DCKR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP1G80DCKR meets industry standards.
7.What is the process for return or replacement of SN74AUP1G80DCKR?
All SN74AUP1G80DCKR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP1G80DCKR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP1G80DCKR part is unused and in its original packaging.
Return procedure for SN74AUP1G80DCKR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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