Texas Instruments SN74AUP1G97DRLRG4
- Part No.:
- SN74AUP1G97DRLRG4
- Manufacturer:
- Texas Instruments
- Package:
- SOT-563, SOT-666
- Datasheet:
-
SN74AUP1G97DRLRG4.pdf
- Description:
- IC CONF MULTI-FUNC GATE SOT-563
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74AUP1G97DRLRG4 from Texas Instruments is a low-power configurable multiple-function gate IC in SOT-5X3 (DRL) package, supporting eight logic functions (MUX, AND, OR, NAND, NOR, inverter, noninverter) via 3-bit input control (A/B/C). It operates from 0.8 V to 3.6 V, delivers 5.6 ns max propagation delay at 3.3 V, and features Schmitt-trigger inputs for noise immunity in battery-powered portable systems.
For engineers reviewing the SN74AUP1G97DRLRG4 datasheet, SN74AUP1G97DRLRG4 pinout, SN74AUP1G97DRLRG4 application, or SN74AUP1G97DRLRG4 equivalent, key selection criteria include its ultra-low static current (0.9 mA max), 1.5 pF typical input capacitance, Ioff support for partial-power-down mode, and compatibility with mixed-mode 3.6-V I/O signaling in space-constrained point-to-point designs.
Technical Context
The SN74AUP1G97DRLRG4 implements a single configurable logic cell with three user-defined inputs (A, B, C) and one output (Y), where the function is selected by the 3-bit pattern applied to C/B/A per the truth table. Its Schmitt-trigger inputs provide hysteresis (ΔVT = 0.79 V typ at 3 V), enabling robust operation with slow-rising signals and high noise margin.
It uses TI's AUP (Advanced Ultra-Low-Power) logic family architecture, optimized for sub-1-V operation while maintaining rail-to-rail output swing and 3.6-V I/O tolerance. The Ioff circuitry actively disables outputs during power-down, preventing backflow current when VCC = 0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - supports direct interface with 1.2-V, 1.8-V, 2.5-V, and 3.3-V logic domains without level shifters. |
| tpd Max | 5.6 ns at 3.3 V, CL = 5 pF - enables timing-critical signal routing in high-speed digital interfaces. |
| ICC Max | 0.9 mA at VCC = 3.6 V - extends battery life in always-on sensor nodes and wearables. |
| CI Typ | 1.5 pF - minimizes capacitive loading on driving nets, preserving signal integrity in dense PCB layouts. |
| Ioff Support | Enabled - allows safe insertion into live backplanes or hot-swap subsystems without damaging current flow. |
| Hysteresis ΔVT | 0.79 V at VCC = 3 V - rejects up to ±395 mV of input noise, critical for noisy industrial or automotive environments. |
| ESD Rating | 2000-V HBM, 1000-V CDM - meets JEDEC JESD22-A114-B and JESD22-C101 for robust handling in manufacturing. |
Pinout & Package
SOT-5X3 (DRL) package: 1.7 mm × 1.5 mm × 0.6 mm body, 6-pin surface-mount, lead-free NiPdAu finish, moisture sensitivity level 1 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | A | Data input A for logic configuration; referenced in function table as LSB of control word. |
| 2 | B | Data input B; middle bit of 3-bit function select; Schmitt-triggered for noise rejection. |
| 3 | GND | Ground reference for all internal logic and I/O; must be connected before VCC for proper power sequencing. |
| 4 | Y | Configurable logic output; drives CMOS loads up to ±4 mA at 3 V with rail-to-rail swing. |
| 5 | C | Control input C; MSB of 3-bit function select; determines logic mode (e.g., C=H selects MUX or OR variants). |
| 6 | VCC | Power supply input; decoupling capacitor (0.1 µF) required within 2 mm for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable Logic | Eight selectable functions (MUX, AND, OR, NAND, NOR, inverter, buffer) via static A/B/C inputs - reduces BOM count and board area vs. discrete gates. |
| Schmitt-Trigger Inputs | ΔVT ≥ 0.79 V at 3 V - eliminates need for external hysteresis components in slow-switching sensor interfaces. |
| Ultra-Low Power | ICC ≤ 0.9 mA max across full VCC range - enables multi-year operation on coin-cell batteries in IoT endpoints. |
| Mixed-Mode I/O Tolerance | 3.6-V tolerant inputs at any VCC (0.8–3.6 V) - simplifies interoperation between legacy 3.3-V peripherals and new low-voltage MCUs. |
| Partial-Power-Down Support | Ioff ≤ 0.6 µA at VCC = 0 V - prevents backfeed in modular systems where subsystems power up/down independently. |
Applications
| Industrial Sensor Interface | Wearable Health Monitor |
|---|---|
Use Scenario: Interfacing analog sensor outputs with slow slew rates (e.g., thermistor, humidity) to an MCU ADC input. IC Role / Device Role / Timing Role: Configured as noninverted buffer with Schmitt-trigger input to clean up noisy, slow-rising analog switch signals before digitization. Use Value: Eliminates external RC filtering and comparator stages, reducing component count by 3+ parts while improving ESD robustness (2000-V HBM). | Use Scenario: Managing button debouncing and LED driver enable logic in compact wearable devices powered by 1.8-V Li-ion cells. IC Role / Device Role / Timing Role: Configured as 2-input AND gate to combine wake-on-button and motion-detection signals before waking the main SoC. Use Value: Draws only 0.5 µA typical ICC at 1.8 V, extending battery runtime beyond 6 months in standby mode. |
| Automotive Body Control Module | Low-Power IoT Edge Node |
Use Scenario: Implementing fail-safe logic for door lock status validation using two independent sensor inputs. IC Role / Device Role / Timing Role: Configured as 2-input NAND gate with one inverted input to detect mismatch between latch and striker sensors. Use Value: Operates reliably over –40°C to +85°C with <10% VCC overshoot/undershoot, meeting AEC-Q100 stress requirements without derating. | Use Scenario: Enabling/disabling RF transceiver power based on environmental trigger (e.g., motion + light detection). IC Role / Device Role / Timing Role: Configured as 2-to-1 multiplexer selecting between PIR and ambient light sensor outputs to control transceiver enable line. Use Value: Supports 0.8-V minimum VCC, allowing direct connection to energy-harvesting PMIC outputs without LDO overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G97DRLR | Higher ICC (max 10 µA at 3.3 V), no Schmitt-trigger inputs, 1.65–5.5 V VCC range. | Lacks hysteresis; unsuitable for slow/slew-limited inputs; better for higher-voltage mixed-signal systems. | Select when interfacing with 5-V peripherals and noise immunity is not required. |
| SN74AHC1G97DCKR | Higher speed (tpd = 3.5 ns @ 3.3 V), no Ioff, 2–5.5 V VCC range, no 0.8-V operation. | Cannot operate below 2 V; lacks partial-power-down capability; higher dynamic power (Cpd = 8 pF). | Select when maximum speed is critical and system operates exclusively above 2 V with stable power rails. |
Compared with SN74LVC1G97DRLR and SN74AHC1G97DCKR, the SN74AUP1G97DRLRG4 uniquely combines sub-1-V operation, Schmitt-trigger noise immunity, and Ioff-enabled hot-swap safety-making it the only choice for ultra-low-power, noise-prone, or modular power-domain designs.
Availability
SN74AUP1G97DRLRG4 is available at Aetrix Electronics and suitable for industrial sensor interfaces, wearable health monitors, automotive body control modules, and low-power IoT edge nodes requiring stable component supply and long-term lifecycle support.
Supply support for SN74AUP1G97DRLRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in low-power design and automotive-grade reliability.
The SN74AUP1G97DRLRG4 belongs to TI's Advanced Ultra-Low-Power (AUP) logic family, engineered specifically for battery-operated portable electronics where extended runtime, small footprint, and robust signal integrity are mandatory.
FAQ
What logic functions does the SN74AUP1G97DRLRG4 support?
The SN74AUP1G97DRLRG4 supports eight configurable logic functions: 2-to-1 data selector (MUX), 2-input AND, 2-input OR with one inverted input, 2-input NAND with one inverted input, 2-input AND with one inverted input, 2-input NOR with one inverted input, 2-input OR, inverter, and noninverted buffer. Function selection is determined by the 3-bit combination applied to inputs C, B, and A per the device's truth table.
Does the SN74AUP1G97DRLRG4 require external pull-up or pull-down resistors on unused inputs?
No - all unused inputs of the SN74AUP1G97DRLRG4 must be held at VCC or GND to ensure proper device operation, but external resistors are not required if the controlling logic actively drives them. TI's application report SCBA004 confirms that floating CMOS inputs can cause increased ICC and potential oscillation; tying unused pins directly to supply rails satisfies this requirement without added components.
Can the SN74AUP1G97DRLRG4 be used in a 0.8-V system with guaranteed timing performance?
Yes - the SN74AUP1G97DRLRG4 is fully specified down to 0.8 V VCC, with tpd = 23.1 ns (max) at 0.8 V and CL = 5 pF. Its AUP family architecture maintains functional correctness and timing predictability across the entire 0.8–3.6 V range, making it suitable for energy-harvesting and ultra-low-voltage microcontroller applications where other logic families fail to operate.
What is the significance of Ioff support in the SN74AUP1G97DRLRG4?
The Ioff feature in the SN74AUP1G97DRLRG4 disables output drivers when VCC = 0 V, limiting off-state current to ≤0.6 µA. This prevents damaging backflow current through the device when it is powered down while other system components remain active - a critical capability for hot-pluggable modules, modular power domains, and systems with staggered power sequencing.
Is the SN74AUP1G97DRLRG4 RoHS-compliant and lead-free?
Yes - the SN74AUP1G97DRLRG4 is RoHS-compliant and lead-free, with NiPdAu lead finish. Per TI's Package Option Addendum, it carries MSL Level-1 rating (unlimited floor life at ≤30°C/60% RH) and is qualified for reflow at 260°C peak, meeting IPC/JEDEC standards for modern electronics assembly.
SN74AUP1G97DRLRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- SOT-563, SOT-666
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-5X3
SN74AUP1G97DRLRG4 FAQ
1.How can I place an order for SN74AUP1G97DRLRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP1G97DRLRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP1G97DRLRG4 reliable?
The price and inventory of SN74AUP1G97DRLRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP1G97DRLRG4 is usually 5 days.
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5.How can I obtain technical support or documentation for SN74AUP1G97DRLRG4?
For technical support, including SN74AUP1G97DRLRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP1G97DRLRG4 requirements.
6.How does Aetrix verify that SN74AUP1G97DRLRG4 is sourced from the original manufacturer or authorized distributors?
All SN74AUP1G97DRLRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP1G97DRLRG4 meets industry standards.
7.What is the process for return or replacement of SN74AUP1G97DRLRG4?
All SN74AUP1G97DRLRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP1G97DRLRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP1G97DRLRG4 part is unused and in its original packaging.
Return procedure for SN74AUP1G97DRLRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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