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Texas Instruments SN74AUP1G97DSFR
- Part No.:
- SN74AUP1G97DSFR
- Manufacturer:
- Texas Instruments
- Package:
- 6-XFDFN
- Datasheet:
-
SN74AUP1G97DSFR.pdf
- Description:
- IC GATE MULT-FUNC CONFIG 6SON
- Quantity:
- Payment:
- Shipping:
Inventory:15,974
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Product details
Overview
SN74AUP1G97DSFR from Texas Instruments is a low-power configurable multiple-function gate in a 6-pin SON (DSF) package, operating across 0.8 V to 3.6 V supply range. It implements eight logic functions-including 2-to-1 MUX, AND, OR, NAND, NOR, inverter, and noninverter-via three select inputs (A, B, C), features Schmitt-trigger inputs for noise immunity, and delivers 5.6 ns max propagation delay at 3.3 V for point-to-point signal routing in portable battery-powered systems.
For engineers reviewing the SN74AUP1G97DSFR datasheet, SN74AUP1G97DSFR pinout, SN74AUP1G97DSFR application, or SN74AUP1G97DSFR equivalent, key selection criteria include its ultra-low ICC (0.9 mA max), 1.5 pF typical input capacitance, Ioff support for partial-power-down mode, 3.6-V I/O tolerance, and compatibility with mixed-voltage interfaces in space-constrained embedded designs.
Technical Context
The SN74AUP1G97DSFR uses a single-stage CMOS logic architecture with configurable truth-table mapping driven by three independent inputs (A, B, C), where output Y is determined by all eight combinations per the function table. Its Schmitt-trigger inputs provide hysteresis (ΔVT = 0.79 V typ at 3 V), enabling robust operation with slow-rising or noisy signals.
It supports full rail-to-rail input/output swing, includes Ioff circuitry to isolate outputs during power-down, and maintains stable timing performance across –40°C to 85°C with CL = 5–30 pF loads. The device is not a level shifter but relies on VCC-referenced thresholds and 3.6-V-tolerant I/O for mixed-mode interfacing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - enables direct interface with 1.2 V, 1.8 V, 2.5 V, and 3.3 V logic domains without external level translation |
| tpd (Max) | 5.6 ns at 3.3 V, CL = 5 pF - ensures sub-6 ns signal path latency for high-speed control and data selection |
| ICC (Max) | 0.9 mA at 3.6 V - minimizes quiescent current draw in always-on subsystems of battery-powered devices |
| CI (Typ) | 1.5 pF - reduces capacitive loading on driving nets, preserving signal integrity in dense PCB layouts |
| Ioff Support | Yes - prevents back-current flow when VCC = 0 V, allowing safe hot-insertion and partial power-down in multi-rail systems |
| Input Hysteresis | 0.79 V typ at 3 V - improves noise margin against ground bounce and crosstalk in noisy environments |
| ESD Rating | 2000-V HBM, 1000-V CDM - meets industrial-grade ESD robustness requirements without external protection |
Pinout & Package
SN74AUP1G97DSFR is housed in a 6-pin SON (DSF) package measuring 1.16 mm × 1.16 mm × 0.5 mm (max height), with wettable flank leads for automated optical inspection (AOI) and enhanced solder joint reliability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Data/Input Select | Primary logic input; combined with B and C to define one of eight output functions per truth table |
| 2 (B) | Data/Input Select | Secondary logic input; determines output state jointly with A and C under Schmitt-trigger thresholding |
| 3 (C) | Function Control | Select line that configures logic mode (e.g., C = L → Y = B; C = H → Y = A in MUX mode) |
| 4 (GND) | Ground Reference | Return path for all internal logic and I/O; must be low-impedance for stable hysteresis and noise immunity |
| 5 (Y) | Configurable Output | Single-ended CMOS output delivering rail-to-rail swing; drives up to ±4 mA at 3 V |
| 6 (VCC) | Supply Input | Power rail for core logic and I/O buffers; supports 0.8–3.6 V with 3.6-V I/O tolerance |
Key Features
| Feature | Design Value |
|---|---|
| Configurable Logic Function | Eight user-selectable modes (MUX, AND, OR, NAND, NOR, inverter, buffer) via 3-bit input coding - eliminates need for multiple discrete gates |
| Schmitt-Trigger Inputs | Hysteresis ≥0.79 V at 3 V - rejects sub-microsecond noise spikes and enables reliable switching with slow-edge microcontroller GPIOs |
| Nano-Power Operation | ICC ≤ 0.9 mA max across full VCC range - extends battery life in wearables, IoT sensors, and remote controls |
| Mixed-Voltage I/O Tolerance | 3.6-V tolerant inputs/outputs at VCC = 0.8–3.6 V - simplifies interconnection between 1.8 V SoCs and 3.3 V peripherals |
| Partial-Power-Down Support | Ioff limits leakage to ≤0.6 mA when VCC = 0 - prevents bus contention and backfeeding in powered-down subsystems |
Applications
| USB-C Port Controller Logic | Low-Power Sensor Hub Interface |
|---|---|
Use Scenario: Configuring signal routing between USB-C CC lines and MCU GPIOs during plug orientation detection and role negotiation. IC Role / Device Role / Timing Role: Single-gate logic configurator implementing MUX and inverter functions to adapt CC1/CC2 polarity and voltage levels. Use Value: Reduces BOM count vs. discrete logic; enables fast (<6 ns) reconfiguration during real-time USB PD state machine transitions. | Use Scenario: Interfacing multiple analog sensor outputs (e.g., temperature, humidity, accelerometer) to a low-power MCU with limited GPIO resources. IC Role / Device Role / Timing Role: Programmable signal selector and level translator between 1.8 V sensor domain and 3.3 V MCU I/O. Use Value: Eliminates need for separate level shifters and logic gates; Schmitt inputs tolerate slow-slew sensor signals without added RC filtering. |
| Portable Medical Device Power Sequencing | Industrial PLC Input Conditioning |
Use Scenario: Enabling controlled startup sequencing of RF transceiver, display driver, and ADC subsystems in handheld diagnostic tools. IC Role / Device Role / Timing Role: Configurable enable gate with hysteresis, used as a debounced power-good arbiter feeding reset logic. Use Value: Guarantees clean, glitch-free enable signals despite noisy supply ramp-up; operates down to 0.8 V for ultra-low-voltage brownout detection. | Use Scenario: Conditioning 24 V digital inputs into clean 3.3 V logic levels for microcontroller capture, in harsh factory-floor environments. IC Role / Device Role / Timing Role: Input buffer with Schmitt-trigger action, converting slow/noisy industrial signals into deterministic logic edges. Use Value: Replaces external RC + comparator circuits; 1.5 pF CI minimizes trace stub effects; Ioff prevents backfeed during controller firmware updates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G97DSFR | Higher ICC (10 µA typ vs. 0.9 mA max), wider VCC range (1.65–5.5 V), no Ioff, no Schmitt inputs | Better suited for 5 V legacy systems; lacks partial-power-down capability and noise immunity for battery-critical use | Choose when interfacing with 5 V logic and power efficiency is secondary to voltage range |
| SN74AUP2G07DBVR | Dual non-inverting buffer (no configuration), same VCC range and ultra-low power, but fixed function only | Provides identical power profile and size for simple buffering; cannot replace logic selection or MUX functionality | Choose only if application requires two independent buffers without configurability |
Compared with SN74LVC1G97DSFR and SN74AUP2G07DBVR, the SN74AUP1G97DSFR uniquely combines ultra-low static/dynamic power, Schmitt-trigger noise immunity, Ioff-enabled power gating, and eight programmable logic modes in a 1.16 mm × 1.16 mm SON package - making it the sole option for compact, battery-sensitive designs requiring adaptive logic behavior.
Availability
SN74AUP1G97DSFR is available at Aetrix Electronics and suitable for USB-C interface design, portable medical diagnostics, industrial sensor conditioning, and low-power IoT edge node development requiring stable component supply and long-term manufacturability.
Supply support for SN74AUP1G97DSFR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in power management and signal chain solutions.
The AUP family, including SN74AUP1G97DSFR, was designed specifically for ultra-low-power portable electronics - optimizing static and dynamic power across 0.8–3.6 V operation while maintaining signal integrity and mixed-voltage interoperability.
FAQ
What logic functions does the SN74AUP1G97DSFR support?
The SN74AUP1G97DSFR supports eight configurable logic functions: 2-to-1 data selector (MUX), 2-input AND, 2-input OR with one inverted input, 2-input NAND with one inverted input, 2-input AND with one inverted input, 2-input NOR with one inverted input, 2-input OR, inverter, and noninverted buffer. These are selected via the three input pins A, B, and C per the function table in the datasheet. Each configuration is implemented in hardware without internal registers or programming overhead.
Does the SN74AUP1G97DSFR require external pull-up or pull-down resistors on unused inputs?
Yes - all unused inputs of the SN74AUP1G97DSFR must be held at VCC or GND to ensure proper device operation and prevent floating nodes that could cause excessive current draw or undefined output states. This requirement is explicitly stated in the TI datasheet's Recommended Operating Conditions section and applies regardless of whether Schmitt-trigger inputs are used.
What is the maximum load capacitance the SN74AUP1G97DSFR can drive while maintaining specified tpd?
The SN74AUP1G97DSFR's propagation delay is characterized up to CL = 30 pF, with tpd = 7.3 ns max at 3.3 V. Driving loads beyond 30 pF will increase delay nonlinearly and may degrade edge rate; for loads >30 pF, designers should verify timing margins using IBIS models or bench measurement. The device's 4.8 pF typical power dissipation capacitance (Cpd) reflects its optimized drive strength for point-to-point routing.
Can the SN74AUP1G97DSFR be used as a level shifter between 1.8 V and 3.3 V domains?
No - the SN74AUP1G97DSFR is not a bidirectional level shifter. While its inputs are 3.6-V tolerant and it operates from VCC = 0.8–3.6 V, its output swing is referenced to VCC. To translate between 1.8 V and 3.3 V logic, VCC must be set to the target output voltage (e.g., 3.3 V), and input signals must stay within VI = 0–3.6 V. It does not provide automatic voltage-domain isolation or direction control.
Is the SN74AUP1G97DSFR pin-compatible with other 6-pin SON logic gates from TI?
No - the SN74AUP1G97DSFR uses a unique pinout (A-B-C-GND-Y-VCC) specific to its configurable function implementation. It is not pin-compatible with standard gates like SN74AUP1G04DSFR (inverter) or SN74AUP1G08DSFR (AND), which follow different pin assignments. Layout reuse requires verification against each device's mechanical drawing and top-view diagram.
SN74AUP1G97DSFR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- 6-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- Yes
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-SON (1x1)
SN74AUP1G97DSFR FAQ
1.How can I place an order for SN74AUP1G97DSFR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP1G97DSFR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP1G97DSFR reliable?
The price and inventory of SN74AUP1G97DSFR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP1G97DSFR is usually 5 days.
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Once your SN74AUP1G97DSFR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP1G97DSFR?
For technical support, including SN74AUP1G97DSFR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP1G97DSFR requirements.
6.How does Aetrix verify that SN74AUP1G97DSFR is sourced from the original manufacturer or authorized distributors?
All SN74AUP1G97DSFR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP1G97DSFR meets industry standards.
7.What is the process for return or replacement of SN74AUP1G97DSFR?
All SN74AUP1G97DSFR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP1G97DSFR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP1G97DSFR part is unused and in its original packaging.
Return procedure for SN74AUP1G97DSFR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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