Texas Instruments SN74AUP1G98YFPR

Overview

SN74AUP1G98YFPR from Texas Instruments is a low-power configurable multiple-function logic gate in a 6-pin YFP (NanoStar™ WCSP) package. It operates across 0.8 V to 3.6 V, delivers 5.3 ns max propagation delay at 3.3 V, features Schmitt-trigger inputs for noise immunity, and supports eight logic configurations (MUX, AND, OR, NAND, NOR, inverter, noninverter) via three input pins - ideal for space-constrained battery-powered sensor interfaces and portable I/O expansion.

For engineers reviewing the SN74AUP1G98YFPR datasheet, SN74AUP1G98YFPR pinout, SN74AUP1G98YFPR application, or SN74AUP1G98YFPR equivalent, key selection criteria include its ultra-low ICC (0.9 mA max), 1.5 pF typical input capacitance, Ioff support for partial-power-down mode, 3.6-V I/O tolerance, and compatibility with mixed-voltage signal routing in wearables and IoT edge nodes.

Technical Context

The SN74AUP1G98YFPR implements a single configurable gate using CMOS AUP technology optimized for sub-1-V operation. Its 3-bit input control (A, B, C) selects one of eight combinational logic functions, with output Y determined by the truth table. All inputs accept slow-rising signals due to integrated Schmitt-trigger hysteresis (ΔVT up to 1.31 V at 3 V).

It supports partial-power-down via Ioff circuitry that disables outputs when VCC = 0 V, preventing backflow current. Input thresholds (VT+ and VT−) are voltage-scalable across the full 0.8–3.6 V VCC range, enabling reliable interfacing with diverse logic families without level shifters.

Key Specifications

Pinout & Package

SN74AUP1G98YFPR uses a 6-ball NanoStar™ WCSP (YFP) package with 0.23-mm large solder bumps, measuring 1.05 mm × 1.05 mm × 0.4 mm max height. The die-as-package construction minimizes parasitic inductance and footprint.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar configurable logic gate applications.

Compared with SN74LVC1G98DBVR, SN74AUP1G98YFPR provides superior noise immunity and lower dynamic power at sub-2-V operation, while SN74AUP1G57DBVR offers functional overlap with reduced feature set - both require validation of logic mode mapping and timing margins in target applications.

Availability

SN74AUP1G98YFPR is available at Aetrix Electronics and suitable for wearable electronics, battery-powered sensor nodes, and portable medical devices requiring stable component supply, long-term lifecycle support, and ultra-small-footprint logic integration.

Supply support for SN74AUP1G98YFPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with decades of automotive, industrial, and consumer design expertise.

The AUP logic family targets ultra-low-power portable applications, delivering industry-leading static and dynamic power efficiency across 0.8–3.6 V while maintaining robust signal integrity and mixed-voltage interoperability.

FAQ

What logic functions does the SN74AUP1G98YFPR support?

The SN74AUP1G98YFPR supports eight configurable logic functions: 2-to-1 multiplexer with inverted output, 2-input NAND, 2-input NOR with one inverted input, 2-input AND with one inverted input, 2-input NAND with one inverted input, 2-input OR with one inverted input, 2-input NOR, noninverted buffer, and inverter. Selection is determined by the three input pins A, B, and C per the function table in the datasheet. Each configuration is implemented in hardware and requires no programming or configuration registers.

Does the SN74AUP1G98YFPR support partial-power-down operation?

Yes, the SN74AUP1G98YFPR includes Ioff circuitry that disables outputs when VCC = 0 V, preventing damaging current backflow through the device during power sequencing or hot-swap events. This feature is fully specified per JESD 78 Class II latch-up standards and enables safe use in multi-rail systems where subsystems power up/down independently - a critical capability for battery-backed systems using SN74AUP1G98YFPR.

What is the maximum propagation delay for SN74AUP1G98YFPR at 1.8 V?

At VCC = 1.8 V ± 0.15 V and CL = 5 pF, the maximum propagation delay (tpd) for SN74AUP1G98YFPR is 7.2 ns across the full operating temperature range (–40°C to 85°C). This value is measured from any input (A, B, or C) to output Y under standard load conditions and reflects worst-case timing for timing-critical signal routing in low-voltage applications using SN74AUP1G98YFPR.

Can SN74AUP1G98YFPR interface directly with 3.3-V logic while powered from 1.2 V?

Yes, SN74AUP1G98YFPR has 3.6-V I/O tolerance on all inputs and outputs, meaning it can safely accept 3.3-V signals even when VCC is as low as 1.2 V. This eliminates the need for external level-shifting components in mixed-voltage designs - for example, connecting a 3.3-V MCU GPIO to SN74AUP1G98YFPR's input while powering the device from a 1.2-V rail in an energy-harvesting sensor node.

What package type and dimensions does SN74AUP1G98YFPR use?

SN74AUP1G98YFPR uses the YFP package: a 6-ball NanoStar™ wafer-chip-scale package with 0.23-mm large solder bumps. Its footprint is 1.05 mm × 1.05 mm, height is ≤ 0.4 mm, and ball pitch is 0.4 mm. This ultra-compact package enables high-density PCB layouts in space-constrained applications such as hearing aids and smart patches where SN74AUP1G98YFPR is deployed.