Texas Instruments SN74AUP1T97YFPR
- Part No.:
- SN74AUP1T97YFPR
- Manufacturer:
- Texas Instruments
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
SN74AUP1T97YFPR.pdf
- Description:
- IC TRANSLATOR UNIDIR 6DSBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74AUP1T97YFPR from Texas Instruments is a single-supply voltage-level translator IC with configurable logic functionality, supporting 1.8 V ↔ 2.5 V and 1.8 V ↔ 3.3 V bidirectional translation at VCC = 2.5 V or 3.3 V, featuring Schmitt-trigger inputs (ΔVT = 210 mV), Ioff protection (0.5 µA), and ultra-low static power (0.9 µA max). It enables compact interface bridging in battery-powered IoT sensor nodes.
For engineers reviewing the SN74AUP1T97YFPR datasheet, SN74AUP1T97YFPR pinout, SN74AUP1T97YFPR application, or SN74AUP1T97YFPR equivalent, key selection criteria include its 6-pin DSBGA (YFP) package, 2.3 V–3.6 V supply range, nine programmable gate functions via input biasing, and verified 4 mA output drive capability for clean signal integrity in mixed-voltage microcontroller peripherals.
Technical Context
The SN74AUP1T97YFPR implements AUP ultra-low-power logic architecture optimized for battery-backed systems, with hysteresis-based Schmitt-trigger inputs rejecting noise on slow-rising analog-digital interface lines. Its single-VCC design eliminates need for dual supplies while maintaining LVCMOS-compatible thresholds across 1.8 V, 2.5 V, and 3.3 V domains.
Logic configuration is achieved by hardwiring inputs A, B, and C to VCC or GND per the Function Selection Table, enabling nine discrete functions-including 2-to-1 MUX, AND, OR, NAND, NOR, inverter, and buffer-without external components. Ioff support allows safe operation during partial power-down with 0 V VCC and up to 3.6 V applied to I/O pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3 V to 3.6 V - accommodates battery voltage droop in portable devices without functional interruption |
| Input Threshold Hysteresis | 210 mV (ΔVT) - ensures robust noise immunity on noisy PCB traces or long flex cables |
| Ioff Leakage | 0.5 µA max at VCC = 0 V - prevents backfeeding and enables hot-swap compatibility in modular systems |
| Output Drive | ±4 mA - reduces overshoot/undershoot on 50 Ω transmission lines, eliminating need for series termination resistors |
| Propagation Delay | 1.6 ns min (VCC = 3.3 V, VI = 1.8 V, CL = 5 pF) - supports >100 MHz data rates in level-shifted control paths |
| Power Dissipation Capacitance | 5 pF at VCC = 3.3 V - contributes to sub-1 µW static power consumption in always-on wake-up circuits |
| ESD Rating | 2000 V HBM - meets industrial IEC 61000-4-2 system-level surge immunity requirements |
Pinout & Package
SN74AUP1T97YFPR uses a 6-pin DSBGA (YFP) package measuring 1.0 mm × 1.4 mm with 0.4 mm pitch, optimized for space-constrained wearable and medical sensor modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A) | Configurable logic input | Biasing determines gate function; accepts 0–3.6 V regardless of VCC state due to Ioff |
| 2 (B) | Configurable logic input | Used with A and C to select one of nine logic modes per Function Selection Table |
| 3 (GND) | Ground reference | Provides return path for all internal logic and output current; must be low-impedance for noise immunity |
| 4 (C) | Configurable logic input / select control | In 2-to-1 MUX mode, selects between A and B inputs; tied high/low to configure logic behavior |
| 5 (VCC) | Single power supply | Supplies core logic and output drivers; range 2.3–3.6 V enables direct Li-ion or regulated 3.3 V rail connection |
| 6 (Y) | Configurable logic output | Delivers rail-to-rail CMOS output with 4 mA drive; Schmitt-trigger input stage ensures clean transitions |
Key Features
| Feature | Design Value |
|---|---|
| Nine configurable gate functions | Eliminates need for multiple discrete logic ICs-single part replaces SN74AUP1G00, SN74AUP1G02, SN74AUP1G04, etc., reducing BOM count and layout area |
| Schmitt-trigger inputs | 210 mV hysteresis rejects EMI-induced glitches on shared PCB traces, critical for reliable wake-up signaling in low-power sleep modes |
| Ioff partial-power-down support | Enables safe isolation of powered-down subsystems (e.g., sensor array) while main MCU remains active-no external isolation switches required |
| Ultra-low static power | 0.9 µA max ICC enables multi-year battery life in coin-cell-powered remote sensors operating at <1 µA average current |
| DSBGA YFP package | 1.0 mm × 1.4 mm footprint with 0.4 mm pitch fits within tight spacing constraints of hearing aids and implantable device PCBs |
Applications
| IoT Sensor Node Interface | Wearable Biometric Monitor |
|---|---|
|
Use Scenario: Bridging 1.8 V MEMS accelerometer outputs to 3.3 V microcontroller GPIO with minimal board area. IC Role / Device Role / Timing Role: Voltage-level translator and logic configurator-configured as noninverted buffer to pass interrupt signals without inversion. Use Value: Eliminates need for separate level shifter + buffer ICs; 0.9 µA ICC extends CR2032 battery life beyond 3 years in periodic-readout mode. |
Use Scenario: Interfacing 2.5 V optical heart-rate sensor to 1.8 V ultra-low-power MCU in smartwatch firmware. IC Role / Device Role / Timing Role: Bidirectional level translator with Schmitt-trigger input-configured as 2-input AND gate to combine sensor ready and MCU ready signals. Use Value: 210 mV hysteresis suppresses noise from switching DC-DC converters; DSBGA YFP package fits beneath curved OLED display bezel. |
| Medical Patch Device | Industrial Wireless Transceiver |
|
Use Scenario: Level-shifting ECG analog front-end control signals (1.8 V) to 3.3 V RF SoC in disposable patch monitor. IC Role / Device Role / Timing Role: Single-supply translator with Ioff-enables safe power sequencing where RF section powers down before analog section. Use Value: 0.5 µA Ioff prevents leakage-induced drift in precision analog signal paths during standby; RoHS-compliant SnAgCu solder finish ensures biocompatibility. |
Use Scenario: Configuring logic for antenna switch control in sub-GHz LoRa module with mixed 3.3 V digital and 2.5 V RF sections. IC Role / Device Role / Timing Role: Programmable gate-set as 2-to-1 MUX to route either MCU or watchdog reset signal to RF transceiver enable pin. Use Value: Reduces component count vs. discrete transistor MUX; 4 mA drive ensures fast edge rates on 50 Ω PCB trace to antenna switch. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar voltage-level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AUP1T98DBVR | Same AUP family, but fixed inverter function only; no configurable logic; identical VCC range and Ioff spec | Lacks nine-function flexibility-suitable only when inverter-only behavior is required | Select SN74AUP1T98DBVR if board space permits SOT-23 and logic function is static; otherwise retain SN74AUP1T97YFPR for configurability |
| TXS0102DQMR | Auto-direction sensing, 2-channel, higher drive (8 mA), but higher ICC (10 µA) and larger 10-pin VSSOP package | Requires no direction-control pin but consumes 10× more quiescent current-unsuitable for battery-critical designs | Choose TXS0102DQMR only for high-speed bidirectional data buses (e.g., I²C); avoid for low-duty-cycle control signals where SN74AUP1T97YFPR's 0.9 µA ICC is decisive |
Compared with SN74AUP1T98DBVR and TXS0102DQMR, SN74AUP1T97YFPR uniquely balances ultra-low power (0.9 µA), logic configurability (9 functions), and minimal footprint (1.0 mm × 1.4 mm DSBGA), making it optimal for space- and energy-constrained embedded control interfaces rather than high-throughput data channels.
Availability
SN74AUP1T97YFPR is available at Aetrix Electronics and suitable for IoT sensor node interface, wearable biometric monitor, and medical patch device applications requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for SN74AUP1T97YFPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in power-efficient IC design.
The SN74AUP1T97YFPR belongs to TI's AUP ultra-low-power logic family, engineered specifically for battery-operated and energy-harvesting systems where nanowatt static power and flexible logic configuration are essential for extended operational lifetime.
FAQ
What voltage translation combinations does the SN74AUP1T97YFPR support?
The SN74AUP1T97YFPR supports 1.8 V ↔ 2.5 V and 1.8 V ↔ 3.3 V bidirectional level translation when VCC is set to 2.5 V or 3.3 V respectively. It does not support 2.5 V ↔ 3.3 V translation. Input thresholds are designed to accept standard LVCMOS levels: VIH(min) = 0.75 V at VCC = 3.3 V and VIL(max) = 0.5 V, ensuring reliable switching across these combinations. The SN74AUP1T97YFPR achieves this using Schmitt-trigger inputs with 210 mV hysteresis for noise margin.
How is logic functionality configured on the SN74AUP1T97YFPR?
Logic functionality on the SN74AUP1T97YFPR is configured by hardwiring its three inputs-A, B, and C-to either VCC or GND, per the Function Selection Table in the datasheet. This selects one of nine discrete functions including 2-to-1 MUX, AND, OR, NAND, NOR, inverter, and buffer. No external programming or clock is needed-the configuration is static and determined at power-up. The SN74AUP1T97YFPR's pinout and truth table ensure deterministic behavior without firmware overhead.
Does the SN74AUP1T97YFPR require external pull-up or pull-down resistors?
No, the SN74AUP1T97YFPR does not require external pull-up or pull-down resistors for normal operation. All unused inputs must be actively tied to VCC or GND to prevent floating states that could increase ICC or cause undefined output behavior. The device's internal design ensures stable logic states without external biasing, and its Ioff feature maintains high-impedance isolation even when VCC = 0 V. This simplifies layout and reduces component count compared to alternatives requiring external resistors.
What is the thermal performance of the SN74AUP1T97YFPR in its YFP package?
The SN74AUP1T97YFPR in the 6-pin DSBGA (YFP) package has a junction-to-ambient thermal resistance (RθJA) of 123 °C/W, measured under JEDEC JESD51-7 conditions. This value reflects efficient heat dissipation through the package's exposed die attach pad and solder joints. At maximum recommended load (4 mA output current) and ambient temperature of 85 °C, junction temperature rise remains below 30 °C above ambient-well within the –40 °C to 85 °C operating range. The SN74AUP1T97YFPR's ultra-low power consumption further minimizes self-heating.
Is the SN74AUP1T97YFPR compatible with lead-free reflow processes?
Yes, the SN74AUP1T97YFPR is fully compatible with lead-free reflow processes. It carries an MSL Level-1 rating with peak reflow temperature of 260 °C, and its YFP package uses SnAgCu (SAC305) ball metallurgy. The device meets RoHS Directive 2011/65/EU requirements and is qualified for standard JEDEC J-STD-020D.2 reflow profiles, including ramp-to-spike and soak profiles. Aetrix Electronics guarantees full compliance with IPC-A-610 Class 2 standards for all SN74AUP1T97YFPR shipments.
SN74AUP1T97YFPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Translator Type:
- Voltage Level
- Channel Type:
- Unidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 1
- Voltage - VCCA:
- 1.8 V ~ 2.7 V
- Voltage - VCCB:
- 2.3 V ~ 3.6 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Single-Ended
- Data Rate:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- Configurable Gate Logic Functions
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XFBGA, DSBGA
SN74AUP1T97YFPR FAQ
1.How can I place an order for SN74AUP1T97YFPR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP1T97YFPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP1T97YFPR reliable?
The price and inventory of SN74AUP1T97YFPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP1T97YFPR is usually 5 days.
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SN74AUP1T97YFPR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AUP1T97YFPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP1T97YFPR?
For technical support, including SN74AUP1T97YFPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP1T97YFPR requirements.
6.How does Aetrix verify that SN74AUP1T97YFPR is sourced from the original manufacturer or authorized distributors?
All SN74AUP1T97YFPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP1T97YFPR meets industry standards.
7.What is the process for return or replacement of SN74AUP1T97YFPR?
All SN74AUP1T97YFPR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP1T97YFPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP1T97YFPR part is unused and in its original packaging.
Return procedure for SN74AUP1T97YFPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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