Texas Instruments SN74AUP2G126YZPR
- Part No.:
- SN74AUP2G126YZPR
- Manufacturer:
- Texas Instruments
- Package:
- 8-XFBGA, DSBGA
- Datasheet:
-
SN74AUP2G126YZPR.pdf
- Description:
- IC BUF NON-INVERT 3.6V 8DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:4,538
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Product details
Overview
SN74AUP2G126YZPR from Texas Instruments is a dual 3-state bus buffer gate optimized for ultra-low-power operation across 0.8 V to 3.6 V supply range, featuring 9.9 ns max propagation delay at 3.3 V, 1.5 pF typical input capacitance, and Ioff support for partial-power-down mode. It enables bidirectional signal isolation in space-constrained portable electronics such as wearables and IoT sensor nodes.
For engineers reviewing the SN74AUP2G126YZPR datasheet, SN74AUP2G126YZPR pinout, SN74AUP2G126YZPR application, or SN74AUP2G126YZPR equivalent, key selection criteria include its 0.9 μA max ICC at 3.6 V, 3.6-V I/O tolerance for mixed-voltage interfacing, input-disable capability for floating inputs, and DSBGA YZP package with 0.23-mm solder bumps.
Technical Context
This device implements two independent noninverting buffers, each with active-high output-enable (OE) control enabling high-impedance (Z) state on associated Y outputs. Its AUP family architecture delivers sub-1-μA static current across full VCC range while maintaining robust noise immunity via input hysteresis and <10% VCC overshoot/undershoot.
The SN74AUP2G126YZPR supports point-to-point signaling only - not bus loading - and uses Ioff circuitry to block reverse current during power-down, ensuring system-level safety in multi-rail environments. Its input-disable feature permits unconnected inputs without leakage-induced logic faults.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - supports single-supply operation across battery voltage decay in coin-cell and Li-ion systems |
| tpd Max | 9.9 ns at 3.3 V, CL = 5 pF - enables timing-critical interface bridging up to ~50 MHz data rates |
| ICC Max | 0.9 μA at 3.6 V - extends battery life in always-on sensor monitoring applications |
| Input Capacitance | 1.5 pF typical - minimizes capacitive loading on driving sources and preserves signal edge integrity |
| Ioff | 0.6 μA max at 0 V - prevents backflow current when powered down, critical for hot-swap and rail sequencing |
| IOH/IOL | –4 mA / +4 mA at 3 V - sufficient drive strength for short PCB traces and low-capacitance loads |
| ESD Rating | 2000-V HBM, 1000-V CDM - meets industrial handling requirements without external protection |
Pinout & Package
SN74AUP2G126YZPR uses an 8-ball DSBGA (YZP) package measuring 1.5 mm × 1.5 mm × 0.5 mm max height, with Pb-free SnAgCu solder bumps and ball pitch of 0.35 mm. The exposed die pad is electrically isolated and must be left open or connected to secondary GND.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 2A | Input A for Buffer 1 / Buffer 2 | Noninverting data inputs accepting 0.8–3.6 V logic levels; tolerate 3.6 V regardless of VCC |
| 1Y, 2Y | Output Y for Buffer 1 / Buffer 2 | 3-state noninverting outputs; high-Z when corresponding OE is low |
| 1OE, 2OE | Output Enable for Buffer 1 / Buffer 2 | Active-high control; drives Y to Z-state when low; supports floating input disable when unconnected |
| VCC | Power Supply | Single supply rail; powers both buffers and internal logic; requires local 100-nF decoupling |
| GND | Ground Reference | Return path for all currents; must be low-impedance; no internal connection to exposed pad |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low ICC | 0.9 μA max at 3.6 V enables >10-year battery life in maintenance-free IoT endpoints |
| 3.6-V I/O Tolerance | Allows direct interface with 3.3-V or 2.5-V peripherals without level shifters in mixed-voltage domains |
| Input-Disable Function | Permits unconnected inputs without false triggering or increased leakage - simplifies board layout and reduces BOM |
| Ioff Partial-Power-Down | Blocks current flow between powered/unpowered rails, preventing damage during staggered power sequencing |
| NanoStar™ DSBGA | 1.5 mm × 1.5 mm footprint saves >70% board area vs. SOIC-8; ideal for ultra-compact wearable designs |
Applications
| Wearable Health Monitor | Industrial Sensor Node |
|---|---|
Use Scenario: Isolating I²C or SPI signals between ultra-low-power MCU and analog front-end ICs in a wrist-worn ECG module. IC Role / Device Role / Timing Role: Dual-directional signal buffer with independent 3-state control per channel, enabling selective peripheral wake-up without disturbing other subsystems. Use Value: 0.9 μA ICC extends coin-cell battery life beyond 2 years; 1.5 pF input capacitance preserves rise/fall times on 100-kHz sensor data lines. | Use Scenario: Level-shifting and isolation between a 1.8-V microcontroller and 3.3-V environmental sensor array in a factory-floor wireless node. IC Role / Device Role / Timing Role: Voltage-tolerant bus driver providing bidirectional signal conditioning and rail decoupling during partial power-down events. Use Value: 3.6-V I/O tolerance eliminates discrete level translators; Ioff prevents backfeed when MCU sleeps while sensors remain active. |
| Portable Medical Diagnostic Tool | Smart Home Edge Controller |
Use Scenario: Enabling/disabling communication paths between multiple ADCs and a central processor in a handheld ultrasound probe. IC Role / Device Role / Timing Role: Dual-channel 3-state gate managing time-multiplexed analog data routing with precise enable timing control. Use Value: 9.9 ns tpd ensures sub-100-ns channel switching latency; input hysteresis rejects noise on long flex-cable interconnects. | Use Scenario: Signal buffering between a 3.3-V Wi-Fi SoC and multiple 1.8-V GPIO-expander ICs in a battery-powered smart thermostat. IC Role / Device Role / Timing Role: Low-leakage interface isolator supporting hot-plug detection and dynamic rail management. Use Value: Input-disable allows unused expander ports to float safely; NanoStar™ package fits within 2.0 mm × 2.0 mm keep-out zone on dense RF layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DCUR | Higher ICC (10 μA typ), wider tpd range (3.5–11 ns), VCC min = 1.65 V | Not suitable for sub-1.65 V battery operation; better drive strength for heavier loads | Select when higher output current (>8 mA) or legacy VSSOP footprint required |
| SN74AUC2G126YZPR | Faster tpd (2.3 ns typ at 2.5 V), narrower VCC range (0.8–2.7 V), no Ioff | Cannot interface with 3.3-V peripherals; lacks partial-power-down protection | Select only for speed-critical 1.8-V-only systems where rail sequencing is controlled externally |
Compared with SN74LVC2G126DCUR and SN74AUC2G126YZPR, the SN74AUP2G126YZPR uniquely balances ultra-low static power, 3.6-V I/O tolerance, and Ioff - making it the sole choice for battery-operated mixed-voltage systems requiring long-term reliability and rail independence.
Availability
SN74AUP2G126YZPR is available at Aetrix Electronics and suitable for wearable health monitors, industrial sensor nodes, portable medical diagnostic tools, and smart home edge controllers requiring stable component supply and long-lifecycle support.
Supply support for SN74AUP2G126YZPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog and embedded processing solutions, with leadership in low-power logic, precision analog, and high-reliability interface ICs.
The AUP family - including SN74AUP2G126YZPR - was designed specifically for battery-powered portable electronics, delivering industry-leading static/dynamic power efficiency without compromising signal integrity or noise immunity.
FAQ
What is the maximum operating temperature range for SN74AUP2G126YZPR?
The SN74AUP2G126YZPR is fully specified for operation from –40°C to +85°C ambient temperature. This range is validated per JEDEC JESD47 stress testing and applies across the full 0.8 V to 3.6 V VCC range. Thermal performance is further enhanced by the YZP package's 102°C/W θJA rating, enabling reliable use in sealed enclosures without forced airflow.
Does SN74AUP2G126YZPR support true bidirectional data flow?
No - the SN74AUP2G126YZPR is a dual noninverting buffer with unidirectional signal path (A → Y). Each channel has independent 3-state control via its own OE input, allowing either output to be disabled independently, but it does not provide automatic direction sensing or bus arbitration. For bidirectional applications, separate transmit/receive paths or dedicated transceivers like SN74AUP2G241 are required.
Can SN74AUP2G126YZPR be used with a 0.8-V supply rail?
Yes - the SN74AUP2G126YZPR is fully functional at VCC = 0.8 V, with guaranteed parameters including tpd ≤ 19.2 ns (CL = 5 pF), VIH ≤ 0.65 × VCC, and VOL ≤ 0.3 × VCC. This makes it uniquely suited for energy-harvesting and ultra-low-voltage battery systems where supply drops below 1.0 V during discharge cycles.
Is the exposed center pad on SN74AUP2G126YZPR required to be connected?
No - the exposed center pad on SN74AUP2G126YZPR must be left electrically open or connected only as a secondary GND. It has no internal electrical connection to VCC or GND. TI explicitly states that connecting it to any voltage rail other than GND may compromise thermal or electrical performance, and no thermal benefit is gained from soldering it to a thermal pad.
How does the input-disable feature work on SN74AUP2G126YZPR?
The input-disable feature on SN74AUP2G126YZPR allows A and OE inputs to float without causing undefined logic states or excessive leakage. When an input is left unconnected, internal circuitry clamps leakage to <0.5 μA and prevents oscillation - verified across –40°C to +85°C. This eliminates need for pull-up/down resistors on unused channels, reducing BOM count and PCB area in multi-buffer designs.
SN74AUP2G126YZPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- 8-XFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DSBGA
SN74AUP2G126YZPR FAQ
1.How can I place an order for SN74AUP2G126YZPR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP2G126YZPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of SN74AUP2G126YZPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP2G126YZPR is usually 5 days.
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Once your SN74AUP2G126YZPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP2G126YZPR?
For technical support, including SN74AUP2G126YZPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP2G126YZPR requirements.
6.How does Aetrix verify that SN74AUP2G126YZPR is sourced from the original manufacturer or authorized distributors?
All SN74AUP2G126YZPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP2G126YZPR meets industry standards.
7.What is the process for return or replacement of SN74AUP2G126YZPR?
All SN74AUP2G126YZPR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP2G126YZPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP2G126YZPR part is unused and in its original packaging.
Return procedure for SN74AUP2G126YZPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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