Texas Instruments SN74AUP2G79DQER
- Part No.:
- SN74AUP2G79DQER
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 8-XFDFN
- Datasheet:
-
SN74AUP2G79DQER.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 8X2SON
- Quantity:
- Payment:

- Shipping:

Inventory:2,248
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Product details
Overview
SN74AUP2G79DQER from Texas Instruments is a dual positive edge-triggered D-type flip-flop in an 8-pin X2SON (DQE) package, operating from 0.8 V to 3.6 V supply. It delivers 4 ns maximum propagation delay at 3.3 V, 0.9 µA max static current, and 3 pF typical dynamic power capacitance-optimized for ultra-low-power point-to-point logic in portable battery-powered systems.
For engineers reviewing the SN74AUP2G79DQER datasheet, SN74AUP2G79DQER pinout, SN74AUP2G79DQER application, or SN74AUP2G79DQER equivalent, key selection criteria include its Ioff partial-power-down support, 1.5 pF input capacitance, 3.3-V I/O tolerance for mixed-voltage interfacing, and guaranteed operation down to 0.8 V for energy-constrained designs.
Technical Context
This device implements two independent D-type latches, each triggered on the rising edge of CLK with setup/hold times as low as 0.6 ns (3.3 V, CL = 15 pF). Its AUP logic family uses advanced CMOS process technology to achieve sub-1-µA ICC across the full 0.8–3.6 V VCC range while maintaining rail-to-rail output swing and robust noise immunity (<10% VCC overshoot/undershoot).
The Ioff circuitry actively disables outputs during partial power-down, preventing backflow current when VCC = 0 V while inputs remain biased at 0–3.6 V. Input clamp diodes and JESD 78 Class II latch-up compliance (>100 mA) ensure system-level robustness in industrial and portable environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 0.8 V to 3.6 V - enables direct interface with 1.2-V, 1.8-V, 2.5-V, and 3.3-V logic domains without level shifters |
| tpd Max | 4 ns at 3.3 V - supports >250 MHz clock rates in point-to-point timing-critical paths |
| ICC Max | 0.9 µA at 25°C - extends battery life in always-on sensor nodes and wearables |
| Cpd Typ | 3 pF at 3.3 V - reduces dynamic switching power by >60% vs. older AUC/AHC families |
| Ci Typ | 1.5 pF - minimizes capacitive loading on driving gates and improves signal integrity |
| Ioff Support | Yes - blocks current flow when powered down, enabling safe hot-insertion and multi-rail sequencing |
| ESD Rating | 2000-V HBM, 1000-V CDM - meets IEC 61000-4-2 Level 2 for handheld and industrial end equipment |
Pinout & Package
X2SON-8 (DQE) package: 1.45 mm × 1.05 mm, 0.4 mm max height, exposed thermal pad, lead-free NiPdAu finish, moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1CLK | Rising-edge clock input for first flip-flop; accepts 0–3.6 V logic levels with 200 ns/V input transition rate limit |
| 2 | 1D | Data input for first flip-flop; must meet tsu ≥ 0.6 ns (3.3 V) before CLK↑ to guarantee reliable capture |
| 3 | 2Q | Inverted output of second flip-flop; drives loads up to ±4 mA at 3.3 V with VOL ≤ 0.45 V |
| 4 | GND | Ground reference for both flip-flops and internal bias networks; requires low-inductance connection to PCB ground plane |
| 5 | VCC | Primary power supply; decoupling capacitor (0.1 µF) required within 2 mm of pin for stable high-speed operation |
| 6 | 1Q | Non-inverted output of first flip-flop; provides rail-to-rail swing with <10% VCC overshoot/undershoot |
| 7 | 2D | Data input for second flip-flop; electrically isolated from 1D; shares same VCC/GND domain |
| 8 | 2CLK | Rising-edge clock input for second flip-flop; fully independent timing path from 1CLK |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | 0.9 µA max ICC enables multi-year battery life in IoT endpoint devices |
| Wide VCC scalability | 0.8–3.6 V operation allows single BOM across multiple voltage rails in mixed-signal SoC interfaces |
| Ioff partial-power-down | Prevents back-current when VCC = 0 V, supporting hot-plug and power-gating architectures |
| Low-noise switching | Overshoot/undershoot <10% VCC eliminates need for external termination in short trace applications |
| 3.6-V I/O tolerant | Accepts 3.6-V inputs while powered from 1.2 V or 1.8 V - simplifies voltage translation in legacy upgrades |
Applications
| Wireless Sensor Node Timing | Portable Medical Device Logic |
|---|---|
Use Scenario: Synchronizing ADC sampling and RF transmit bursts in BLE/Wi-Fi edge sensors with tight duty-cycle constraints. IC Role / Device Role / Timing Role: Dual-edge-aligned data capture and state holding for low-latency control loops. Use Value: 0.9 µA static current and 4 ns tpd enable microsecond-level response without compromising battery runtime. | Use Scenario: Glucose monitor or pulse oximeter requiring fail-safe data latching during intermittent power cycling. IC Role / Device Role / Timing Role: Reliable storage of calibration flags and sensor status bits across sleep/wake transitions. Use Value: Ioff support prevents leakage-induced corruption when main supply drops to zero between measurements. |
| Industrial PLC I/O Expansion | Wearable Display Interface |
Use Scenario: Isolating and synchronizing digital inputs from 24-V field sensors into 3.3-V microcontroller GPIO banks. IC Role / Device Role / Timing Role: Level-shifting and metastability-hardened input registration stage. Use Value: 3.6-V I/O tolerance and 1.5 pF Ci allow direct connection to optocoupler outputs without external resistors. | Use Scenario: Driving segmented OLED backlight timing signals in smartwatches with aggressive power budgets. IC Role / Device Role / Timing Role: Edge-triggered PWM gating and frame-sync signal distribution. Use Value: Sub-1-µA ICC and 0.4 mm profile minimize board area and quiescent drain in space-constrained wearable PCBs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G79DQER | Higher ICC (10 µA typ), wider VCC (1.65–5.5 V), no Ioff, 5 ns tpd at 3.3 V | Better suited for 5-V legacy systems; lacks partial-power-down capability | Select when interfacing with 5-V peripherals and lowest static power is not critical |
| 74AUP2G79GMH | Same AUP family, but in 8-pin MicroPak (G) package; identical electrical specs | Smaller footprint (1.35 × 1.35 mm), no thermal pad; lower thermal performance | Select when board space is more constrained than thermal requirements |
Compared with SN74LVC2G79DQER, SN74AUP2G79DQER offers 11× lower static current and Ioff support for power-gated systems; compared with 74AUP2G79GMH, it provides superior thermal dissipation via the DQE package's exposed pad-critical for sustained high-frequency operation in sealed enclosures.
Availability
SN74AUP2G79DQER is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical devices, industrial I/O modules, and wearable display interfaces requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for SN74AUP2G79DQER includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in power efficiency and signal integrity.
The AUP logic family-including SN74AUP2G79DQER-is engineered specifically for ultra-low-power portable electronics, delivering industry-leading static/dynamic power trade-offs across sub-1-V to 3.6-V operation without sacrificing speed or noise immunity.
FAQ
What is the minimum supply voltage for reliable operation of SN74AUP2G79DQER?
The SN74AUP2G79DQER is fully specified from 0.8 V to 3.6 V. At 0.8 V, it guarantees functional operation with fmax ≥ 48 MHz and tpd ≤ 20.3 ns (CL = 15 pF), making it suitable for energy-harvesting and coin-cell-powered applications where supply voltage may dip below 1.0 V during peak load.
Does SN74AUP2G79DQER support partial power-down mode?
Yes, SN74AUP2G79DQER includes Ioff circuitry that disables outputs when VCC = 0 V, preventing damaging back-current flow even if inputs remain at 0–3.6 V. This feature is explicitly tested per JESD 78 and supports safe multi-rail sequencing in battery-backed systems.
What is the maximum clock frequency supported by SN74AUP2G79DQER at 3.3 V?
At 3.3 V and CL = 15 pF, SN74AUP2G79DQER achieves fmax = 280 MHz (typical) and 260 MHz (guaranteed min). With lighter loads (CL = 5 pF), it sustains up to 280 MHz (min) - sufficient for high-speed serial data alignment and real-time control loop sampling.
How does the X2SON (DQE) package of SN74AUP2G79DQER differ from the DCU or RSE variants?
SN74AUP2G79DQER uses the 1.45 mm × 1.05 mm X2SON package with an exposed thermal pad, offering lower θJA (261°C/W) than DCU (220°C/W) and RSE (253°C/W). Its 0.4 mm max height and NiPdAu finish support fine-pitch assembly and improved thermal performance in thermally dense layouts.
Can SN74AUP2G79DQER drive standard 50-Ω transmission lines directly?
No, SN74AUP2G79DQER is not designed for 50-Ω line driving. Its output drive strength (±4 mA at 3.3 V) targets point-to-point loads with CL ≤ 30 pF. For 50-Ω traces, use a dedicated line driver or add series termination; the device's low Ci (1.5 pF) and clean edges minimize reflections in short, unterminated interconnects.
SN74AUP2G79DQER Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- 8-XFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Standard
- Type:
- D-Type
- Output Type:
- Non-Inverted
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 266 MHz
- Max Propagation Delay @ V, Max CL:
- 6.3ns @ 3.3V, 30pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Iq):
- 500 nA
- Input Capacitance:
- 1.5 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-X2SON (1.4x1)
SN74AUP2G79DQER FAQ
1.How can I place an order for SN74AUP2G79DQER through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP2G79DQER on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP2G79DQER reliable?
The price and inventory of SN74AUP2G79DQER are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP2G79DQER is usually 5 days.
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Once your SN74AUP2G79DQER order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP2G79DQER?
For technical support, including SN74AUP2G79DQER datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP2G79DQER requirements.
6.How does Aetrix verify that SN74AUP2G79DQER is sourced from the original manufacturer or authorized distributors?
All SN74AUP2G79DQER products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP2G79DQER meets industry standards.
7.What is the process for return or replacement of SN74AUP2G79DQER?
All SN74AUP2G79DQER units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP2G79DQER, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP2G79DQER part is unused and in its original packaging.
Return procedure for SN74AUP2G79DQER:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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