Texas Instruments SN74AUP2G79YFPR
- Part No.:
- SN74AUP2G79YFPR
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 8-XFBGA, DSBGA
- Datasheet:
-
SN74AUP2G79YFPR.pdf
- Description:
- IC FF D-TYPE DUAL 1BIT 8DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,919
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Product details
Overview
SN74AUP2G79YFPR from Texas Instruments is a dual positive edge-triggered D-type flip-flop in ultra-low-power AUP logic family, operating from 0.8 V to 3.6 V supply. It delivers 4 ns maximum propagation delay at 3.3 V, 0.9 µA max static current, and 3 pF typical dynamic power capacitance. Used for clock-synchronized data latching in portable battery-powered systems.
For engineers reviewing the SN74AUP2G79YFPR datasheet, SN74AUP2G79YFPR pinout, SN74AUP2G79YFPR application, or SN74AUP2G79YFPR equivalent, key selection criteria include Ioff-enabled partial-power-down support, 1.5 pF input capacitance, 3.3-V I/O tolerance for mixed-voltage interfacing, and YFP (NanoStar™ WCSP) package compatibility with high-density PCB layouts.
Technical Context
This device implements two independent D-type flip-flops, each triggered on the rising edge of CLK with setup/hold times as low as 0.6 ns (3.3 V, CL = 15 pF). Its AUP logic architecture achieves sub-1-µA ICC across full VCC range while maintaining rail-to-rail output swing and robust noise immunity (overshoot/undershoot <10% VCC).
Designed for point-to-point signal integrity, it features Ioff circuitry that disables outputs during power-down to prevent backflow current, and supports 3.6-V tolerant I/Os enabling seamless interfacing with higher-voltage logic domains without level shifters.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 0.8 V to 3.6 V - enables single-supply operation across ultra-low-voltage microcontrollers and mixed-voltage SoC interfaces |
| Max Propagation Delay | 3.6 ns at 3.3 V (CL = 15 pF) - ensures tight timing margins in high-speed data capture paths |
| Static Current (ICC) | 0.9 µA maximum - extends battery life in always-on sensor nodes and wearables |
| Input Capacitance (Ci) | 1.5 pF typical - minimizes loading on driving gates and preserves signal rise/fall times |
| Ioff Support | Yes - prevents current backflow when powered down, critical for hot-swappable or multi-rail power sequencing |
| IO Tolerance | 3.6-V I/O tolerant - allows direct connection to 3.3-V or 2.5-V buses without external level translation |
| Operating Temperature | –40°C to +85°C - qualified for industrial and automotive cabin applications |
Pinout & Package
NanoStar™ WCSP (YFP) 8-bump wafer chip-scale package, 0.23-mm large bump, Pb-free, 1.35 mm × 1.35 mm footprint, 0.4 mm max height. Exposed die pad for thermal conduction and mechanical stability.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | VCC | Primary power supply input - must be decoupled locally with 0.1 µF ceramic capacitor |
| 2 | 1Q | Output of first flip-flop - non-inverting, edge-triggered data latch |
| 3 | 2D | Data input to second flip-flop - sampled on rising edge of 2CLK |
| 4 | 1CLK | Clock input for first flip-flop - rising-edge sensitive, VIH/VIL thresholds scale with VCC |
| 5 | 1D | Data input to first flip-flop - sampled on rising edge of 1CLK |
| 6 | 2Q | Output of second flip-flop - non-inverting, synchronized to 2CLK |
| 7 | GND | Ground reference - connected to PCB ground plane under die for optimal EMI performance |
| 8 | 2CLK | Clock input for second flip-flop - electrically isolated from 1CLK; supports independent clock domains |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low static power | 0.9 µA max ICC enables >10-year battery life in coin-cell-powered IoT endpoints |
| Rail-to-rail output swing | VOH ≥ VCC – 0.1 V and VOL ≤ 0.1 V at 3.3 V ensures full logic-level compatibility with downstream CMOS inputs |
| Sub-1.5 pF input capacitance | Reduces capacitive loading by >50% vs. standard AUC/AHC families, preserving signal integrity at >100 MHz |
| Ioff partial-power-down | Disables outputs when VCC = 0 V, eliminating backfeed risk in multi-supply systems with staggered power sequencing |
| 3.6-V tolerant I/Os | Permits direct interface with 3.3-V peripherals even when VCC = 1.2 V - eliminates need for discrete level shifters |
Applications
| Wireless Sensor Node Timing | Low-Power MCU Interface |
|---|---|
Use Scenario: Synchronizing ADC sample triggers and RF transmit enable pulses in BLE/Wi-Fi sensor hubs. IC Role / Device Role / Timing Role: Dual DFF provides independent, glitch-free clock-domain crossing between MCU core clock and peripheral timing domains. Use Value: 0.9 µA static current extends coin-cell lifetime beyond 5 years; Ioff prevents leakage during sleep modes. | Use Scenario: Latching GPIO status or interrupt flags before MCU wake-up in deep-sleep mode. IC Role / Device Role / Timing Role: Edge-triggered storage element captures asynchronous events with precise timing alignment to system clock. Use Value: 1.5 pF Ci minimizes trace loading; 3.6-V I/O tolerance allows direct connection to 3.3-V sensors without voltage translation. |
| Portable Medical Monitor Data Capture | Industrial Control Signal Conditioning |
Use Scenario: Capturing ECG waveform samples at precise intervals in handheld diagnostic devices. IC Role / Device Role / Timing Role: Dual flip-flop acts as synchronous sampler and pipeline register for analog front-end digital outputs. Use Value: 4 ns tpd at 3.3 V enables sampling rates up to 250 MSPS; –40°C to +85°C rating supports clinical environment operation. | Use Scenario: Debouncing push-button inputs and synchronizing PLC control signals in factory automation panels. IC Role / Device Role / Timing Role: Positive-edge DFF provides metastability-hardened input registration for noisy industrial environments. Use Value: Latch-up immunity >100 mA per JESD78 Class II ensures reliability in ESD-prone settings; 0.8 V min VCC supports brown-out resilience. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74AUP2G74YFPR | Dual D-type flip-flop with complementary Q and Q̅ outputs per stage; higher pin count (8-pin YFP same), no Ioff | Required when inverted output needed without external inverter; unsuitable for partial-power-down use cases | Select SN74AUP2G79YFPR when only true-Q outputs and Ioff are required; choose SN74AUP2G74YFPR if Q̅ is needed per channel |
| SN74LVC2G74DCTR | Higher ICC (10 µA typ), 1.65–5.5 V VCC range, no Ioff, larger SC70-8 package (2.0 × 2.1 mm) | Better suited for 5-V legacy systems; lacks power-gating capability and ultra-low ICC optimization | Choose SN74AUP2G79YFPR for battery-critical designs below 3.6 V; select SN74LVC2G74DCTR only when 5-V compatibility or wider VCC margin is mandatory |
Compared with SN74AUP2G74YFPR and SN74LVC2G74DCTR, SN74AUP2G79YFPR uniquely combines sub-1-µA static power, Ioff-enabled power sequencing, and 1.35 mm² NanoStar™ packaging - making it the only option optimized for space-constrained, multi-rail, long-life portable electronics.
Availability
SN74AUP2G79YFPR is available at Aetrix Electronics and suitable for wireless sensor nodes, portable medical monitors, and industrial control interfaces requiring stable component supply and long-term lifecycle assurance.
Supply support for SN74AUP2G79YFPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions for industrial, automotive, and personal electronics markets.
The AUP logic family - including SN74AUP2G79YFPR - was engineered specifically for ultra-low-power, high-integration portable applications where battery life, board area, and mixed-voltage interoperability are critical design constraints.
FAQ
What is the maximum clock frequency supported by SN74AUP2G79YFPR at 3.3 V?
At 3.3 V and CL = 15 pF, SN74AUP2G79YFPR supports a maximum clock frequency of 260 MHz. This value is confirmed in the SWITCHING CHARACTERISTICS table (SCES755C, p.7) under "fmax" for VCC = 3.3 V ± 0.3 V. Performance degrades with higher load capacitance - e.g., 240 MHz at CL = 30 pF.
Does SN74AUP2G79YFPR support partial-power-down operation?
Yes, SN74AUP2G79YFPR fully supports partial-power-down via its Ioff circuitry. When VCC = 0 V, the Ioff feature disables all outputs to prevent damaging current backflow from live I/Os into the unpowered device. This is explicitly specified in the FEATURES section and electrical characteristics table (Ioff ≤ 0.6 µA at VCC = 0 V).
What is the pin 1 identifier for SN74AUP2G79YFPR in the YFP package?
In the YFP (NanoStar™ WCSP) package, pin 1 identification for SN74AUP2G79YFPR is indicated by solder-bump composition: a solid dot (•) denotes Pb-free finish. This is documented in the ORDERING INFORMATION section (p.3) and PACKAGE OPTION ADDENDUM (p.1).
Can SN74AUP2G79YFPR operate reliably at 0.8 V supply voltage?
Yes, SN74AUP2G79YFPR is fully specified from 0.8 V to 3.6 V. At 0.8 V, it guarantees fmax ≥ 48 MHz (CL = 15 pF) and tpd ≤ 20.3 ns, with VIH ≤ 0.65 × VCC and VIL ≥ 0.35 × VCC. These values are validated across –40°C to +85°C per RECOMMENDED OPERATING CONDITIONS (p.4).
Is SN74AUP2G79YFPR pin-compatible with other 8-pin AUP dual flip-flops in YFP package?
Yes, SN74AUP2G79YFPR shares identical YFP package dimensions, bump layout, and pinout with SN74AUP2G74YFPR and SN74AUP2G80YFPR - all follow the same NanoStar™ WCSP mechanical drawing (SLAU271). Pin mapping (VCC, GND, CLK/D/Q assignments) is consistent across this YFP-based AUP dual-FF series.
SN74AUP2G79YFPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74AUP
- Package/Case:
- 8-XFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Standard
- Type:
- D-Type
- Output Type:
- Non-Inverted
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 266 MHz
- Max Propagation Delay @ V, Max CL:
- 6.3ns @ 3.3V, 30pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 4mA, 4mA
- Voltage - Supply:
- 0.8V ~ 3.6V
- Current - Quiescent (Iq):
- 500 nA
- Input Capacitance:
- 1.5 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DSBGA
SN74AUP2G79YFPR FAQ
1.How can I place an order for SN74AUP2G79YFPR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74AUP2G79YFPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74AUP2G79YFPR reliable?
The price and inventory of SN74AUP2G79YFPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74AUP2G79YFPR is usually 5 days.
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SN74AUP2G79YFPR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74AUP2G79YFPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74AUP2G79YFPR?
For technical support, including SN74AUP2G79YFPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74AUP2G79YFPR requirements.
6.How does Aetrix verify that SN74AUP2G79YFPR is sourced from the original manufacturer or authorized distributors?
All SN74AUP2G79YFPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74AUP2G79YFPR meets industry standards.
7.What is the process for return or replacement of SN74AUP2G79YFPR?
All SN74AUP2G79YFPR units undergo pre-shipment inspection (PSI). If there is an issue with SN74AUP2G79YFPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74AUP2G79YFPR part is unused and in its original packaging.
Return procedure for SN74AUP2G79YFPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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