Texas Instruments SN74CBT16390DGVR
- Part No.:
- SN74CBT16390DGVR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 56-TFSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBT16390DGVR.pdf
- Description:
- IC MUX/DEMUX 16 X 1:2 56TVSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74CBT16390DGVR from Texas Instruments is a 16-bit to 32-bit FET bus switch with dual-output-enable control, 5-Ω on-state resistance, TTL-compatible inputs, and operation over –40°C to 85°C. It functions as a bidirectional multiplexer/demultiplexer for memory interleaving and PCI bus isolation in embedded computing systems.
For engineers reviewing the SN74CBT16390DGVR datasheet, SN74CBT16390DGVR pinout, SN74CBT16390DGVR application, or SN74CBT16390DGVR equivalent, key selection criteria include its 56-pin TVSOP (DGV) package, dual independent OE control logic, 0.25 ns propagation delay, latch-up immunity (>250 mA), and ESD robustness (2000-V HBM).
Technical Context
This device implements two independent 16-bit bidirectional FET switch arrays sharing a common A-port bus and separate 1B/2B output ports. Its dual OE inputs (OE1, OE2) enable three operational states: A↔1B only, A↔2B only, or A↔1B+2B simultaneously - no internal arbitration or timing overlap required.
Each switch channel features low on-resistance (5–7 Ω at VCC = 4.5 V), minimal charge injection (<0.5 pC), and rail-to-rail analog signal handling capability up to VCC. Input clamping and ESD protection are integrated per JESD 22 standards without external components.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 4.5 V to 5.5 V - ensures compatibility with standard 5-V TTL/CMOS logic domains and stable switching performance across industrial temperature range. |
| On-State Resistance (ron) | 5 Ω typical at VI = 0 V, II = 30 mA - enables low-voltage-drop signal routing with <150 mV drop at 30 mA, critical for high-fidelity bus integrity. |
| Propagation Delay (tpd) | 0.25 ns typical - supports >1 GHz data rates in high-speed parallel bus applications such as PCI slot expansion and memory bank switching. |
| Enable/Disable Time (ten/tdis) | 1.3 ns min / 5.9 ns max - guarantees fast, glitch-free bus arbitration during dynamic port reconfiguration without hold-time violations. |
| Input Clamp Current (IIK) | –50 mA - protects against negative transient events during hot-plug or power sequencing without external diodes. |
| ESD Rating (HBM) | 2000 V - meets IEC 61000-4-2 Level 2 requirements for board-level robustness in industrial and telecom equipment. |
| Latch-Up Immunity | >250 mA per JESD 17 - eliminates risk of destructive latch-up under bus contention or ground bounce conditions. |
Pinout & Package
SN74CBT16390DGVR uses a 56-pin Thin Very Small Outline Package (TVSOP, DGV), 11.4 mm × 4.4 mm × 1.2 mm, JEDEC MO-194 compliant, with exposed pad for thermal enhancement and Q1 pin-1 orientation in tape-and-reel delivery.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1–A16 | Common bidirectional data bus input/output | Shared 16-bit path connecting to both 1B and 2B banks; must be driven by single-source bus driver or terminated appropriately. |
| 1B1–1B16 | First 16-bit bidirectional output port | Connects to first peripheral or memory bank when OE1 = L; electrically isolated when OE1 = H. |
| 2B1–2B16 | Second 16-bit bidirectional output port | Connects to second peripheral or memory bank when OE2 = L; fully isolated when OE2 = H. |
| OE1, OE2 | Independent active-low output enables | Asynchronous control: OE1 enables A↔1B, OE2 enables A↔2B; both low enables simultaneous connection to both banks. |
| VCC, GND (×2 each) | Power supply and ground terminals | Dual VCC/GND pairs reduce switching noise and improve PSRR; require local 0.1 µF ceramic decoupling per pair. |
| NC (Pins 27, 28, 55, 56) | No internal connection | Unbonded pads - must remain unconnected; no routing or soldering required. |
Key Features
| Feature | Design Value |
|---|---|
| 56-pin TVSOP (DGV) footprint | Enables high-density PCB layout with 0.4 mm pitch and 1.2 mm max height - ideal for space-constrained industrial controllers and telecom line cards. |
| Dual independent OE control | Allows dynamic reconfiguration between two 16-bit buses without bus contention or software coordination - reduces FPGA resource usage in PCIe bridge designs. |
| 5 Ω typical on-resistance | Minimizes insertion loss and signal distortion for DC-coupled parallel buses operating up to 100 MHz, preserving eye diagram integrity. |
| TTL-compatible input thresholds | Accepts 2.0 V VIH / 0.8 V VIL - interoperates directly with legacy 5-V microcontrollers, CPLDs, and ASICs without level-shifting circuitry. |
| Integrated 2000-V HBM ESD protection | Eliminates need for external TVS diodes on A/1B/2B lines - reduces BOM count and improves reliability in field-deployed equipment. |
Applications
| Memory Interleaving System | PCI Slot Expansion Hub |
|---|---|
Use Scenario: Two independent DRAM banks are accessed alternately to double effective bandwidth while maintaining single-controller interface. IC Role / Device Role / Timing Role: SN74CBT16390DGVR acts as a time-multiplexed bus coupler, routing controller address/data lines to Bank A or Bank B based on OE1/OE2 state transitions synchronized to memory clock edges. Use Value: Enables 16-bit × 2 bank interleaving without adding latency or requiring additional address decoding logic - achieves 2× throughput gain within same PCB area. |
Use Scenario: A single PCI host interface connects to two downstream PCI slots with independent enable control and hot-swap isolation. IC Role / Device Role / Timing Role: SN74CBT16390DGVR serves as a bidirectional bus isolator, allowing the host to communicate with Slot 1 (OE1 = L), Slot 2 (OE2 = L), or both (OE1 = OE2 = L) without electrical loading or signal reflection. Use Value: Eliminates need for discrete bus buffers or complex PLD-based arbitration - reduces component count and simplifies compliance testing for PCI SIG mechanical specifications. |
| Industrial Backplane Switching | Legacy Bus Signal Multiplexing |
Use Scenario: A programmable logic controller (PLC) backplane routes I/O data between multiple modular CPU and I/O carrier boards via shared parallel bus. IC Role / Device Role / Timing Role: SN74CBT16390DGVR functions as a configurable bus segment selector, enabling one master CPU to access any of two I/O sub-buses using dedicated OE signals tied to FPGA GPIO. Use Value: Provides deterministic, zero-latency bus switching with no setup/hold timing constraints - avoids metastability risks inherent in clock-domain crossing solutions. |
Use Scenario: A microcontroller with limited GPIO drives multiple legacy peripherals (e.g., LCD, EEPROM, ADC) sharing a common 8-bit data bus but requiring separate chip-select timing. IC Role / Device Role / Timing Role: SN74CBT16390DGVR operates in demultiplexer mode: A-port receives MCU data, while 1B/2B ports drive distinct peripheral data buses controlled by OE1/OE2 as chip-select proxies. Use Value: Replaces discrete 74-series logic and discrete MOSFET switches - cuts board area by 60% and eliminates timing skew between peripheral enable paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTD16210DGVR | 32-bit dual-supply (3.3 V/5 V) switch with 3-state outputs; higher Ron (7 Ω), no dual-OE architecture. | Requires level translation for mixed-voltage systems; lacks simultaneous dual-bank connection capability. | Select when interfacing 3.3-V peripherals to 5-V buses; avoid if memory interleaving or PCI dual-slot control is required. |
| 74FST3244QDR | 16-bit dual 8-bit switch in SOIC-48; single OE per 8-bit section; Ron = 6 Ω; no ESD rating specified. | Supports only 8-bit granularity per enable; insufficient pin count for full 16-bit A-port routing. | Use only for cost-sensitive, non-industrial applications where ESD robustness and full 16-bit control are not required. |
Compared with SN74CBT16390DGVR, SN74CBTD16210DGVR adds voltage translation but sacrifices dual-OE flexibility and HBM-rated ESD protection, while 74FST3244QDR offers lower cost but requires two devices to match 16-bit functionality and lacks documented latch-up immunity.
Availability
SN74CBT16390DGVR is available at Aetrix Electronics and suitable for memory interleaving systems, PCI slot expansion hubs, industrial backplane switching, and legacy bus signal multiplexing requiring stable component supply and long-term industrial lifecycle support.
Supply support for SN74CBT16390DGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of leadership in high-speed logic and interface solutions.
The SN74CBT16390DGVR belongs to TI's Widebus™ family of high-performance bus switches, designed specifically for low-latency, low-distortion signal routing in industrial, telecom, and computing infrastructure applications.
FAQ
What is the maximum continuous current rating per channel for SN74CBT16390DGVR?
The SN74CBT16390DGVR supports a continuous channel current of 128 mA per switch path, verified under recommended operating conditions (VCC = 4.5 V to 5.5 V, TA = –40°C to 85°C). This rating ensures reliable operation in high-drive parallel bus applications without thermal derating at full industrial temperature range. Exceeding this current may increase on-resistance and trigger thermal shutdown in sustained overload conditions.
Does SN74CBT16390DGVR support hot-swap operation with live backplane insertion?
Yes, SN74CBT16390DGVR supports hot-swap operation due to its integrated 2000-V HBM ESD protection, latch-up immunity exceeding 250 mA per JESD 17, and robust input clamp current (–50 mA). These features prevent damage during live insertion into powered backplanes, provided OE pins are held inactive (high) until power stabilization and bus initialization complete.
Can SN74CBT16390DGVR operate with 3.3-V control inputs while VCC is at 5 V?
No - SN74CBT16390DGVR requires control inputs (OE1, OE2) to meet TTL-compatible thresholds: VIH ≥ 2.0 V and VIL ≤ 0.8 V at VCC = 5 V. A 3.3-V logic high exceeds VIH but may not guarantee noise margin; use a resistor divider or buffer if driving from 3.3-V sources to ensure reliable low-state detection below 0.8 V.
What is the thermal resistance (θJA) of the SN74CBT16390DGVR in its TVSOP package?
The SN74CBT16390DGVR has a junction-to-ambient thermal resistance (θJA) of 48°C/W in the TVSOP (DGV) package, measured per JESD 51-7 on a standard 4-layer JEDEC test board. This value assumes proper PCB copper pour under the exposed pad; omitting thermal vias increases θJA by up to 15°C/W, potentially limiting sustained 128-mA operation at 85°C ambient.
Are the NC pins on SN74CBT16390DGVR safe to connect to ground or leave floating?
The NC pins (27, 28, 55, 56) on SN74CBT16390DGVR have no internal connection and must remain unconnected - neither grounded nor tied to any voltage. Routing traces to or placing solder on these pins risks shorting adjacent signal lines due to 0.4 mm pitch; TI's package drawings explicitly prohibit termination of NC pads.
SN74CBT16390DGVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBT
- Package/Case:
- 56-TFSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Multiplexer/Demultiplexer
- Circuit:
- 16 x 1:2
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 56-TVSOP
SN74CBT16390DGVR FAQ
1.How can I place an order for SN74CBT16390DGVR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBT16390DGVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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5.How can I obtain technical support or documentation for SN74CBT16390DGVR?
For technical support, including SN74CBT16390DGVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBT16390DGVR requirements.
6.How does Aetrix verify that SN74CBT16390DGVR is sourced from the original manufacturer or authorized distributors?
All SN74CBT16390DGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBT16390DGVR meets industry standards.
7.What is the process for return or replacement of SN74CBT16390DGVR?
All SN74CBT16390DGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBT16390DGVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBT16390DGVR part is unused and in its original packaging.
Return procedure for SN74CBT16390DGVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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