Texas Instruments SN74CBT16861DGGR
- Part No.:
- SN74CBT16861DGGR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 48-TFSOP (0.240", 6.10mm Width)
- Datasheet:
-
SN74CBT16861DGGR.pdf
- Description:
- IC BUS SWITCH 10 X 1:1 48TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:4,143
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Product details
Overview
SN74CBT16861DGGR from Texas Instruments is a 20-bit FET bus switch organized as two independent 10-bit switches, featuring 5-Ω on-state resistance, TTL-compatible control inputs (VIH = 2 V, VIL = 0.8 V), and operation across –40°C to 85°C. It enables high-speed bidirectional signal routing in memory expansion, data multiplexing, and hot-swap I/O buffering applications.
For engineers reviewing the SN74CBT16861DGGR datasheet, SN74CBT16861DGGR pinout, SN74CBT16861DGGR application, or SN74CBT16861DGGR equivalent, key selection criteria include low propagation delay (0.25 ns at 5 V), high-impedance isolation during disable, latch-up immunity (>100 mA per JESD 78 Class II), and TSSOP-48 packaging for space-constrained PCB layouts.
Technical Context
The SN74CBT16861DGGR implements dual 10-bit FET-based analog switches with separate OE controls per bank. Each switch operates as a voltage-controlled pass gate with no internal logic-signal integrity depends solely on Ron (5–7 Ω) and Cio(OFF) (5.5 pF).
It uses standard CMOS process technology with TTL-level input thresholds and supports rail-to-rail analog/digital signal switching up to 5.5 V. No level translation or biasing is required; A/B ports are fully bidirectional and electrically symmetrical.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (Ron) | 5–7 Ω at VCC = 4.5 V, ensuring minimal voltage drop and signal attenuation under 64 mA load. |
| Propagation delay (tpd) | 0.25 ns at VCC = 5 V, enabling sub-nanosecond signal path timing for high-speed bus architectures. |
| Off-state capacitance (Cio) | 5.5 pF, minimizing crosstalk and capacitive loading when the switch is disabled. |
| Supply voltage range | 4 V to 5.5 V - compatible with standard 5-V TTL/CMOS systems without regulation overhead. |
| Input voltage thresholds | VIH = 2 V, VIL = 0.8 V - directly interfaces with legacy TTL outputs without level-shifting circuitry. |
| Latch-up immunity | >100 mA per JESD 78 Class II - ensures robustness against transient current faults in industrial environments. |
| Operating temperature | –40°C to +85°C - qualified for extended industrial temperature range deployment. |
Pinout & Package
TSSOP-48 package (DGG), 12.6 mm × 6.2 mm × 1.2 mm max height, JEDEC MO-153 compliant, lead-free NIPDAU finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A1–1A10, 2A1–2A10 | Port A inputs/outputs (Bank 1 & 2) | Bidirectional signal terminals for first and second 10-bit data paths; electrically identical to B-side pins. |
| 1B1–1B10, 2B1–2B10 | Port B inputs/outputs (Bank 1 & 2) | Paired with corresponding A pins; connection established only when respective OE is low. |
| 1OE, 2OE | Output-enable controls | Active-low enables; each independently gates its 10-bit switch bank - no shared enable logic. |
| VCC (Pins 22, 37) | Power supply | Dual VCC pins reduce IR drop and improve noise immunity across wide bus; must be decoupled locally. |
| GND (Pins 11, 26) | Ground reference | Dual ground pins provide low-inductance return path for both banks; critical for maintaining Ron stability. |
| NC (Pins 1, 48) | No internal connection | Unbonded pads - must remain unconnected; no routing or thermal relief required. |
Key Features
| Feature | Design Value |
|---|---|
| 5-Ω low on-resistance | Enables <10 mV voltage drop at 2 mA, preserving signal swing in 3.3/5-V mixed-voltage backplanes. |
| TTL-compatible control inputs | Eliminates need for external level shifters when driven by legacy 74-series or microcontroller GPIOs. |
| Independent dual-bank enable | Allows selective activation of 10-bit segments - e.g., isolate address vs. data lines without full bus shutdown. |
| High-impedance isolation | Guarantees >10⁹ Ω off-state resistance between ports, preventing leakage-induced contention in shared-bus topologies. |
| Latch-up immunity & ESD protection | Rated >100 mA per JESD 78 Class II and includes internal clamp diodes - suitable for hot-plug and test fixture use. |
Applications
| Memory Expansion Interface | Data Multiplexing |
|---|---|
|
Use Scenario: Adding SRAM or Flash memory to a microcontroller with limited address/data pins. IC Role / Device Role / Timing Role: Bidirectional bus switch isolating main CPU bus from auxiliary memory bus during access arbitration. Use Value: Enables zero-wait-state memory expansion using existing 5-V bus timing, with sub-ns delay preserving setup/hold margins. |
Use Scenario: Sharing a single ADC channel among multiple sensor inputs via time-division multiplexing. IC Role / Device Role / Timing Role: Analog signal path selector routing sensor outputs to ADC input without introducing offset or distortion. Use Value: 5-Ω Ron and 5.5-pF Cio maintain signal fidelity up to 100 MHz, supporting 12-bit+ resolution measurements. |
| Hot-Swap I/O Buffering | Legacy Bus Isolation |
|
Use Scenario: Safely inserting/removing peripheral cards in live 5-V backplane systems. IC Role / Device Role / Timing Role: Signal isolation barrier that prevents backfeeding and bus contention during card insertion. Use Value: High-impedance disable state and latch-up immunity protect host controller from insertion transients and fault currents. |
Use Scenario: Interfacing modern FPGA I/O banks (3.3 V) with legacy 5-V TTL peripherals. IC Role / Device Role / Timing Role: Voltage-agnostic bidirectional pass gate - no level translation needed for DC-coupled signals. Use Value: Maintains signal integrity across voltage domains while avoiding timing skew introduced by active translators. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTD16210DGGR | 24-bit, higher Ron (7–9 Ω), requires 3.3-V-only supply (3.0–3.6 V), no 5-V tolerance. | Suitable for 3.3-V-only systems; not interoperable with 5-V buses or TTL inputs. | Select when operating exclusively in 3.3-V domains and additional bit count is required. |
| 74ALVC164245DGGR | 16-bit dual-supply level shifter (1.65–3.6 V A-side, 2.3–3.6 V B-side), direction-controlled, not bidirectional per pin. | Provides voltage translation but lacks true analog pass-gate behavior and has directional latency asymmetry. | Choose only when explicit level shifting between mismatched voltage domains is mandatory. |
Compared with SN74CBT16861DGGR, SN74CBTD16210DGGR trades 5-V compatibility and lower Ron for higher density, while 74ALVC164245DGGR introduces direction control and voltage translation at the cost of added complexity and reduced analog transparency.
Availability
SN74CBT16861DGGR is available at Aetrix Electronics and suitable for memory expansion, hot-swap I/O buffering, and legacy bus isolation requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant TSSOP packaging.
Supply support for SN74CBT16861DGGR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.
The SN74CBT16861DGGR belongs to TI's Widebus™ family of FET bus switches, designed specifically for low-latency, low-distortion signal routing in industrial, computing, and communications infrastructure where deterministic timing and robustness are critical.
FAQ
What is the maximum continuous current rating per channel for the SN74CBT16861DGGR?
The SN74CBT16861DGGR supports a continuous channel current of 128 mA per switch path, verified under absolute maximum ratings. This allows reliable operation with typical digital bus loads (e.g., 50–100 mA per line in 5-V TTL systems) while maintaining specified on-resistance and thermal performance within the –40°C to 85°C operating range. Exceeding this limit risks thermal runaway or parametric shift in SN74CBT16861DGGR performance.
Does the SN74CBT16861DGGR support bidirectional signal flow on each A–B pair?
Yes, the SN74CBT16861DGGR provides true bidirectional analog/digital signal routing between each A and B terminal pair - no direction pin or internal logic controls signal polarity. The device functions as a passive FET pass gate, meaning voltage and current can flow equally from A to B or B to A when enabled. This behavior is intrinsic to the SN74CBT16861DGGR architecture and confirmed in its functional description and logic diagram.
Can the SN74CBT16861DGGR operate with a 3.3-V supply?
No - the SN74CBT16861DGGR is specified only for 4 V to 5.5 V operation per recommended conditions. At 3.3 V, the device fails to meet VIH/VIL thresholds (2 V/0.8 V), resulting in undefined switching behavior and potential output contention. For 3.3-V systems, TI recommends alternatives like SN74CBTD16210DGGR, but SN74CBT16861DGGR requires strict adherence to its 4–5.5 V supply window.
How does the latch-up immunity of the SN74CBT16861DGGR benefit industrial applications?
The SN74CBT16861DGGR exceeds 100 mA latch-up immunity per JESD 78 Class II, meaning it withstands transient current faults - such as ESD events, power sequencing glitches, or short-duration bus contention - without entering destructive latch-up. This makes SN74CBT16861DGGR suitable for ruggedized industrial controllers, programmable logic systems, and field-deployed equipment where reliability under electrical stress is non-negotiable.
Are the two OE inputs on the SN74CBT16861DGGR functionally isolated?
Yes - 1OE and 2OE are fully independent control inputs, each enabling only its associated 10-bit switch bank (1A↔1B or 2A↔2B). There is no internal coupling or dependency between them. This allows granular bus segmentation - for example, holding memory address lines active while disabling data lines during write cycles - a capability confirmed in the function table and logic diagram of the SN74CBT16861DGGR datasheet.
SN74CBT16861DGGR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBT
- Package/Case:
- 48-TFSOP (0.240", 6.10mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Bus Switch
- Circuit:
- 10 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 48-TSSOP
SN74CBT16861DGGR FAQ
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6.How does Aetrix verify that SN74CBT16861DGGR is sourced from the original manufacturer or authorized distributors?
All SN74CBT16861DGGR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBT16861DGGR meets industry standards.
7.What is the process for return or replacement of SN74CBT16861DGGR?
All SN74CBT16861DGGR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBT16861DGGR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBT16861DGGR part is unused and in its original packaging.
Return procedure for SN74CBT16861DGGR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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