Texas Instruments SN74CBT3384CDGVR
- Part No.:
- SN74CBT3384CDGVR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TFSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBT3384CDGVR.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24TVSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74CBT3384CDGVR from Texas Instruments is a 10-bit TTL-compatible FET bus switch organized as two independent 5-bit bidirectional switches, featuring 3 Ω typical ON-state resistance (ron), near-zero propagation delay (0.15 ns at VCC = 5 V), and undershoot protection up to −2 V on A/B ports - used for PCI interface isolation and memory interleaving in high-speed digital systems.
For engineers reviewing the SN74CBT3384CDGVR datasheet, SN74CBT3384CDGVR pinout, SN74CBT3384CDGVR application, or SN74CBT3384CDGVR equivalent, key selection criteria include Ioff partial-power-down support, 0–5-V data I/O voltage tolerance, 5-pF typical OFF-state input/output capacitance, and TVSOP-24 package compatibility with space-constrained PCB layouts.
Technical Context
The SN74CBT3384CDGVR implements dual 5-bit FET-based analog/digital bus switches with separate 1OE and 2OE control inputs, enabling independent ON/OFF control of each 5-bit segment. Its active undershoot-protection circuitry monitors A/B port voltages and forces switch disable during −2 V transients, preventing false conduction.
Each switch channel operates bidirectionally with near-zero propagation delay due to low ron and minimal Cio(OFF) = 5 pF. The device supports partial-power-down via Ioff, limiting backflow current when VCC = 0 V while maintaining high-impedance isolation between A and B ports.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON-state resistance (ron) | 3 Ω typical - enables low-voltage-drop signal pass-through for 5-V and mixed-voltage (0.8–5-V) I/O systems. |
| Propagation delay (tpd) | 0.15 ns at VCC = 5 V - preserves signal integrity in >1-GHz digital timing paths without added latency. |
| OFF-state I/O capacitance (Cio(OFF)) | 5 pF typical - minimizes capacitive loading and signal distortion on shared buses during isolation. |
| Supply voltage range (VCC) | 4 V to 5.5 V - compatible with standard 5-V logic rails and tolerant of supply droop. |
| Undershoot protection threshold | −2 V on A/B ports - prevents erroneous switching during negative transient events in hot-plug or bus-arbitration scenarios. |
| Ioff leakage at VCC = 0 V | 10 µA max - ensures safe backdrive isolation during system power sequencing or partial shutdown. |
| Input/output voltage range (VI/O) | 0 V to 5.5 V - supports interoperability across 0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V logic families. |
Pinout & Package
SN74CBT3384CDGVR is housed in a 24-pin TVSOP (DGV) package, 4.4 mm × 6.6 mm footprint, 1.2 mm max height, with gull-wing leads and pin 1 index area per JEDEC MO-153. Lead finish is NiPdAu (NIPDAU), MSL Level-1 (unlimited floor life).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE | Output-enable control inputs | Active-low enables respective 5-bit switch segments; OE tied to VCC via pullup ensures high-Z at power-up. |
| 1A1–1A5, 2A1–2A5 | Port A data terminals | First/second 5-bit input/output group; bidirectional signal path when associated OE is low. |
| 1B1–1B5, 2B1–2B5 | Port B data terminals | Corresponding 5-bit output/input group; electrically mirrored to A-side with no direction pin required. |
| VCC, GND | Power and ground | Single 4–5.5 V supply; internal undershoot clamps reference to these rails for protection circuitry. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional zero-delay switching | Enables transparent signal routing between A/B ports without direction control logic or added timing skew. |
| Undershoot protection (−2 V) | Prevents unintended turn-on during negative transients common in PCI, hot-swap, and bus contention events. |
| Ioff partial-power-down support | Blocks damaging current flow when VCC = 0 V, allowing safe operation in multi-rail systems with staggered power sequencing. |
| Low 5-pF OFF-state capacitance | Reduces crosstalk and signal degradation on high-speed buses such as memory address/data lines or peripheral interconnects. |
| TTL/CMOS-compatible control inputs | Accepts 3.3-V or 5-V CMOS and TTL logic levels, eliminating level-shifter requirements for OE signals. |
Applications
| PCI Bus Isolation | Memory Interleaving |
|---|---|
Use Scenario: Isolating PCI add-in card data lines from motherboard during hot-plug insertion or reset sequences. IC Role / Device Role / Timing Role: Bidirectional bus switch providing galvanic isolation with sub-ns delay and −2 V undershoot immunity. Use Value: Prevents bus contention and signal corruption during plug-in events while maintaining full 33-MHz PCI timing compliance. | Use Scenario: Routing address/data between two memory banks in interleaved DRAM architectures. IC Role / Device Role / Timing Role: Low-latency, low-capacitance signal gate enabling simultaneous access to alternating memory blocks. Use Value: Achieves effective bandwidth doubling without adding setup/hold timing overhead or requiring additional clock domains. |
| Low-Distortion Signal Gating | Bus Arbitration Interface |
Use Scenario: Enabling/disabling analog or digital sensor signals in multiplexed data acquisition systems. IC Role / Device Role / Timing Role: Analog-capable FET switch preserving signal fidelity with 3 Ω ron and 5 pF Cio(OFF). Use Value: Maintains <1% gain error and <0.1% THD across DC–100 MHz for precision measurement front-ends. | Use Scenario: Managing shared control bus access among multiple microcontrollers in distributed industrial controllers. IC Role / Device Role / Timing Role: High-impedance isolation switch activated by arbitration logic to prevent bus collisions. Use Value: Guarantees clean bus release with <10 µA Ioff leakage, eliminating need for external pull-ups or bus keepers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTD3384CDGVR | Includes power-down isolation (Ioff) and higher VI/O rating (−0.5 V to 7 V); otherwise identical pinout and function. | Preferred for systems with wider voltage transients or stricter Ioff requirements under full power-off conditions. | Select when robustness against overvoltage beyond −2 V or guaranteed zero-backdrive at VCC = 0 V is mandatory. |
| SN74LVC1G3157DCKR | Single-pole double-throw (SPDT) 2-channel switch; 5-V tolerant, but only 2-bit capacity and 6 Ω ron (typical). | Suitable for point-to-point signal routing, not scalable to 10-bit bus isolation. | Choose only for low-pin-count, low-bandwidth gating where space or cost outweighs bus-width and speed needs. |
Compared with SN74CBT3384CDGVR, SN74CBTD3384CDGVR adds extended voltage fault tolerance and tighter Ioff control, while SN74LVC1G3157DCKR trades bus width and speed for ultra-small SC70 packaging - making SN74CBT3384CDGVR optimal for compact, high-fidelity 10-bit bus isolation where pin count and sub-ns timing are critical.
Availability
SN74CBT3384CDGVR is available at Aetrix Electronics and suitable for PCI interface design, memory subsystem isolation, and industrial bus arbitration requiring stable component supply and long-term manufacturability.
Supply support for SN74CBT3384CDGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with emphasis on reliability, longevity, and industrial-grade performance.
The SN74CBT3384CDGVR belongs to TI's CBT (Crosspoint Bus Transceiver) family, engineered for high-speed, low-distortion digital signal routing in computing, communications, and test equipment where timing integrity and bus robustness are essential.
FAQ
What is the maximum undershoot voltage the SN74CBT3384CDGVR can withstand on its A/B ports?
The SN74CBT3384CDGVR provides active undershoot protection up to −2 V on both A and B ports, as verified in the absolute maximum ratings and undershoot characteristics section of the official datasheet. This protection is implemented via internal sensing circuitry that forces the switch into the OFF state during transient negative excursions, preventing unintended conduction. The SN74CBT3384CDGVR maintains this specification across its full operating temperature range of −40°C to +85°C.
Does the SN74CBT3384CDGVR support mixed-voltage I/O signaling?
Yes, the SN74CBT3384CDGVR supports 0–5-V data I/O signaling, explicitly accommodating 0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V logic families without level shifters. Its VI/O rating of 0 to 5.5 V and rail-to-rail bidirectional operation allow seamless interfacing between disparate voltage domains on the same bus. This capability is intrinsic to the SN74CBT3384CDGVR's FET-switch architecture and confirmed in the recommended operating conditions table.
What is the thermal resistance (θJA) of the SN74CBT3384CDGVR in its TVSOP package?
The SN74CBT3384CDGVR in the TVSOP (DGV) package has a junction-to-ambient thermal resistance (θJA) of 86°C/W, as specified in the absolute maximum ratings table. This value assumes standard JEDEC 2-layer board conditions and is critical for thermal margin calculation in high-density layouts. The SN74CBT3384CDGVR's low ICC (3 µA max) and absence of static power dissipation minimize self-heating, making θJA primarily relevant during sustained high-current switching.
Can the SN74CBT3384CDGVR be used in partial-power-down applications?
Yes, the SN74CBT3384CDGVR fully supports partial-power-down operation via its Ioff feature. When VCC = 0 V, Ioff limits current backflow to ≤10 µA, ensuring safe isolation between powered and unpowered sections of a system. This behavior is tested per JESD 78 Class II latch-up standards and is guaranteed across −40°C to +85°C. The SN74CBT3384CDGVR's Ioff specification eliminates risk of damage during staggered power sequencing in complex embedded platforms.
What is the ON-state resistance (ron) specification for the SN74CBT3384CDGVR?
The SN74CBT3384CDGVR has a typical ON-state resistance (ron) of 3 Ω at VCC = 4.5 V, IO = 30 mA, and VI = 0 V, with a maximum of 6 Ω across all operating conditions. This low ron ensures minimal voltage drop and signal attenuation - especially critical in 5-V and mixed-voltage bus applications. Measured differentially between A and B terminals, ron directly impacts timing skew and power loss, and is a defining parameter of the SN74CBT3384CDGVR's high-fidelity switching performance.
SN74CBT3384CDGVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBT
- Package/Case:
- 24-TFSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TVSOP
SN74CBT3384CDGVR FAQ
1.How can I place an order for SN74CBT3384CDGVR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBT3384CDGVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of SN74CBT3384CDGVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBT3384CDGVR is usually 5 days.
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5.How can I obtain technical support or documentation for SN74CBT3384CDGVR?
For technical support, including SN74CBT3384CDGVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBT3384CDGVR requirements.
6.How does Aetrix verify that SN74CBT3384CDGVR is sourced from the original manufacturer or authorized distributors?
All SN74CBT3384CDGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBT3384CDGVR meets industry standards.
7.What is the process for return or replacement of SN74CBT3384CDGVR?
All SN74CBT3384CDGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBT3384CDGVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBT3384CDGVR part is unused and in its original packaging.
Return procedure for SN74CBT3384CDGVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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