Texas Instruments SN74CBT3384CPW
- Part No.:
- SN74CBT3384CPW
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBT3384CPW.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74CBT3384CPW from Texas Instruments is a high-speed TTL-compatible 10-bit FET bus switch organized as two independent 5-bit bidirectional switches, featuring 3 Ω typical ON-state resistance (ron), near-zero propagation delay (0.15 ns at VCC = 5 V), and undershoot protection up to −2 V on both A and B ports - used for PCI interface isolation and memory interleaving in industrial control backplanes.
For engineers reviewing the SN74CBT3384CPW datasheet, SN74CBT3384CPW pinout, SN74CBT3384CPW application, or SN74CBT3384CPW equivalent, key selection criteria include Ioff partial-power-down support, 0–5-V signal-level compatibility across 1.2-V to 5-V logic families, and TSSOP-24 package thermal performance (θJA = 88°C/W) for dense PCB layouts.
Technical Context
The SN74CBT3384CPW implements dual 5-bit FET-based analog/digital bus switches with separate OE controls (1OE, 2OE), enabling independent enable/disable of each 5-bit segment. Its active undershoot-protection circuitry monitors port voltage and forces OFF-state retention during −2 V transients - critical for hot-swap and mixed-voltage system robustness.
Each switch channel operates bidirectionally with ron = 3 Ω (typ) at VCC = 4.5 V and IO = 30 mA, while maintaining low OFF-state capacitance (Cio(OFF) = 5 pF typ) and ultra-low ICC = 3 µA max - supporting low-noise signal gating without loading adjacent traces or degrading edge integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| ON-state resistance (ron) | 3 Ω typical at VCC = 4.5 V, IO = 30 mA - ensures minimal voltage drop and signal distortion in high-speed data paths. |
| Propagation delay (tpd) | 0.15 ns at VCC = 5 V - enables sub-nanosecond timing alignment for PCI and memory bus applications. |
| Supply voltage range (VCC) | 4 V to 5.5 V - supports stable operation across industrial-grade 5-V rails with ±10% tolerance. |
| Input/output voltage range (VI/O) | 0 V to 5.5 V - allows interoperability with 0.8-V to 5-V logic families without level-shifting circuitry. |
| OFF-state capacitance (Cio(OFF)) | 5 pF typical - minimizes capacitive loading and crosstalk when switching high-frequency signals. |
| Ioff current | 10 µA at VCC = 0 V - prevents backflow current during partial power-down, protecting powered subsystems. |
| Undershoot protection limit | −2 V on A/B ports - maintains OFF-state integrity during transient negative excursions common in hot-plug scenarios. |
Pinout & Package
TSSOP-24 package (PW), 7.9 mm × 4.5 mm × 1.2 mm max height, JEDEC MO-153 compliant, with exposed pad not electrically connected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE | Output-enable control inputs | Active-low enables corresponding 5-bit switch; tied to VCC via pull-up resistor ensures high-impedance at power-up. |
| 1A1–1A5, 2A1–2A5 | Port A data terminals | First/second 5-bit input/output group; bidirectional with no direction pin required. |
| 1B1–1B5, 2B1–2B5 | Port B data terminals | Paired with respective A-group; connected to A when OE is low, isolated when OE is high. |
| GND | Ground reference | Primary return path for all internal circuitry and I/O current; must be low-inductance connection. |
| VCC | Power supply | 4–5.5 V supply for internal biasing and switch control; decoupling capacitor required per datasheet layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional zero-delay switching | Enables transparent data flow between A and B ports without clocking or direction control - ideal for passive bus arbitration. |
| Undershoot protection circuitry | Detects −2 V transients on A/B ports and forces switch OFF, preventing latch-up or false logic states during hot-insertion events. |
| Ioff partial-power-down support | Blocks current flow when VCC = 0 V, allowing safe insertion/removal in live backplanes without disrupting other powered modules. |
| Multi-voltage I/O compatibility | Supports 0.8-V to 5-V signaling levels on data pins - eliminates external level shifters in mixed-supply systems like DDR memory interfaces. |
| Low OFF-capacitance isolation | 5 pF typical Cio(OFF) reduces crosstalk and preserves signal integrity in high-density routing environments such as FPGA mezzanine cards. |
Applications
| PCI Bus Isolation | Memory Interleaving |
|---|---|
|
Use Scenario: Isolating legacy PCI add-in cards from host controller during hot-swap or fault conditions. IC Role / Device Role / Timing Role: Bidirectional bus switch providing galvanic separation and undershoot immunity on 32-bit address/data lines. Use Value: Prevents system lockup during card insertion by blocking −2 V transients and maintaining high-impedance state until full power stabilization. |
Use Scenario: Routing parallel memory banks (e.g., two 16-bit SDRAM channels) to a single 32-bit controller. IC Role / Device Role / Timing Role: Low-ron, zero-delay switch enabling time-aligned access to interleaved memory segments without added latency. Use Value: Delivers 0.15 ns propagation delay and 3 Ω ron to preserve setup/hold margins across 133-MHz memory buses. |
| Industrial Backplane Gating | FPGA I/O Expansion |
|
Use Scenario: Enabling/disabling peripheral modules (e.g., analog I/O, CAN, RS-485) on a modular PLC backplane. IC Role / Device Role / Timing Role: Dual 5-bit switch controlled by FPGA GPIOs to gate bidirectional data and control signals. Use Value: Ioff support allows safe module removal while main CPU remains powered; 5 pF Cio(OFF) prevents signal coupling between inactive slots. |
Use Scenario: Expanding limited FPGA I/O count by sharing pins between configuration and runtime functions (e.g., JTAG + GPIO). IC Role / Device Role / Timing Role: Signal gate isolating debug interface from user logic during normal operation. Use Value: Near-zero tpd avoids timing violations in high-speed FPGA designs; 0–5-V VI/O range matches both 3.3-V configuration and 1.8-V core logic levels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTD3384CPW | Includes bus-hold circuitry on all I/Os; higher ICC = 10 µA max; same ron and pinout. | Required where floating-bus immunity is needed (e.g., unconnected test points); adds ~0.5 ns tpd penalty. | Select SN74CBTD3384CPW only if bus-hold functionality is explicitly required; otherwise SN74CBT3384CPW offers lower power and identical switching performance. |
| SN74LVC1G3157DBVR | Single-pole double-throw (SPDT) analog switch; 5.5 Ω ron; 10 pF Cio(OFF); supports 1.65–5.5 V VCC. | Used for signal routing rather than multi-bit bus isolation; lacks undershoot protection and Ioff. | Choose SN74LVC1G3157DBVR for low-pin-count analog multiplexing; SN74CBT3384CPW remains preferred for 10-bit digital bus isolation with robustness features. |
Compared with SN74CBTD3384CPW and SN74LVC1G3157DBVR, the SN74CBT3384CPW uniquely balances ultra-low ron (3 Ω), −2 V undershoot protection, and Ioff-enabled partial-power-down - making it the only option among the three qualified for hot-swappable PCI and memory interleaving systems requiring simultaneous robustness and speed.
Availability
SN74CBT3384CPW is available at Aetrix Electronics and suitable for PCI interface isolation, memory interleaving, and industrial backplane gating requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant TSSOP packaging.
Supply support for SN74CBT3384CPW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in high-reliability interface and signal-path components.
The SN74CBT3384CPW belongs to TI's CBT (Crossbar Bus Transceiver) logic family, designed specifically for high-speed, low-distortion digital signal routing in computing, communications, and industrial infrastructure equipment.
FAQ
What is the maximum undershoot voltage the SN74CBT3384CPW can tolerate on its A and B ports?
The SN74CBT3384CPW provides active undershoot protection up to −2 V on both A and B ports, as verified in the SCDS132A datasheet Section 6. This feature ensures the switch remains reliably in the OFF state during transient negative excursions, preventing unintended conduction or latch-up in hot-swap applications. The SN74CBT3384CPW achieves this through integrated sensing circuitry that detects undershoot events and disables the internal FETs.
Does the SN74CBT3384CPW support partial-power-down operation, and how is it implemented?
Yes, the SN74CBT3384CPW supports partial-power-down operation via its Ioff feature, which limits current to 10 µA maximum when VCC = 0 V. This design prevents damaging backflow current from live I/O lines into the unpowered device, enabling safe insertion or removal in powered systems. The SN74CBT3384CPW maintains high-impedance isolation between A and B ports under these conditions, as confirmed in the recommended operating conditions table.
What logic families can directly drive the control inputs (1OE, 2OE) of the SN74CBT3384CPW?
The control inputs of the SN74CBT3384CPW accept TTL and 5-V/3.3-V CMOS outputs, with VIH = 2 V min and VIL = 0.8 V max specified over the full temperature range. This allows direct interfacing with standard 74LS, 74HC, and modern microcontroller GPIOs without level translation. The SN74CBT3384CPW also specifies ±1 µA max input leakage (IIN), ensuring minimal loading on driving sources.
What is the typical ON-state resistance (ron) of the SN74CBT3384CPW, and under what conditions is it measured?
The SN74CBT3384CPW has a typical ON-state resistance (ron) of 3 Ω, measured at VCC = 4.5 V, VI = 0 V, and IO = 30 mA per channel, as documented in the electrical characteristics table. This value reflects the lowest resistance achievable across the A–B path when the switch is enabled, contributing to minimal voltage drop and signal attenuation in high-current digital bus applications. The SN74CBT3384CPW maintains ron ≤ 6 Ω across its full operating range.
Is the SN74CBT3384CPW pin-compatible with other members of the CBT3384 family in the same TSSOP-24 package?
Yes, the SN74CBT3384CPW shares identical pinout and footprint with all TSSOP-24 variants of the CBT3384 family, including SN74CBT3384CPWR and SN74CBTD3384CPW. The top-side marking "CU384C" and package drawing PW0024A confirm mechanical and electrical pin equivalence. However, functional differences - such as bus-hold presence in SN74CBTD3384CPW - require verification against schematic intent before substitution. The SN74CBT3384CPW remains the base variant without added features.
SN74CBT3384CPW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBT
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
SN74CBT3384CPW FAQ
1.How can I place an order for SN74CBT3384CPW through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBT3384CPW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBT3384CPW reliable?
The price and inventory of SN74CBT3384CPW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBT3384CPW is usually 5 days.
3.What payment methods are accepted for SN74CBT3384CPW?
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SN74CBT3384CPW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74CBT3384CPW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74CBT3384CPW?
For technical support, including SN74CBT3384CPW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBT3384CPW requirements.
6.How does Aetrix verify that SN74CBT3384CPW is sourced from the original manufacturer or authorized distributors?
All SN74CBT3384CPW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBT3384CPW meets industry standards.
7.What is the process for return or replacement of SN74CBT3384CPW?
All SN74CBT3384CPW units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBT3384CPW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBT3384CPW part is unused and in its original packaging.
Return procedure for SN74CBT3384CPW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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