Texas Instruments SN74CBT6800ADBQR
- Part No.:
- SN74CBT6800ADBQR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SN74CBT6800ADBQR.pdf
- Description:
- IC BUS SW 10 X 1:1 24SSOP/QSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74CBT6800ADBQR from Texas Instruments is a 10-bit FET bus switch with precharged B-port outputs, designed for live-insertion applications in backplane and hot-swap systems. It features 5-Ω on-state resistance, TTL-compatible control inputs, and user-selectable BIASV bias voltage (1.3 V to VCC) to minimize signal distortion during hot-plug events. The device operates from –40°C to 85°C with 4 V to 5.5 V supply voltage.
For engineers reviewing the SN74CBT6800ADBQR datasheet, SN74CBT6800ADBQR pinout, SN74CBT6800ADBQR application, or SN74CBT6800ADBQR equivalent, key selection criteria include bidirectional low-Ron switching, B-port precharge behavior under high-ON disable, thermal performance in TSSOP-24, and compatibility with 3.3-V/5-V mixed-signal buses.
Technical Context
The SN74CBT6800ADBQR implements ten independent NMOS pass-gate switches controlled by a single active-low ON input. When enabled (ON = low), A1–A10 connect bidirectionally to B1–B10 with near-zero propagation delay (0.25 ns typical at 5 V). When disabled (ON = high), the B ports are actively pulled to BIASV via internal ~10-kΩ resistive paths - not floating - enabling noise-suppressed hot insertion.
This architecture avoids charge injection and bus contention during live insertion by eliminating floating nodes. The device requires no external pull-ups on B ports and supports mixed-voltage interfacing: A-side logic levels track VCC (4–5.5 V), while BIASV can be set independently between 1.3 V and VCC, allowing safe interface to lower-voltage subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 3 Ω to 7 Ω (typical 5 Ω at VCC = 4.5 V, VI = 0 V, II = 30 mA) - enables minimal voltage drop and signal integrity across 10-bit data paths |
| Propagation delay (tpd) | 0.25 ns (typical at VCC = 5 V, CL = 50 pF) - supports high-speed parallel bus operation without timing skew penalties |
| Bias voltage range (BIASV) | 1.3 V to VCC - allows configurable precharge level to match downstream logic thresholds (e.g., 1.8 V, 2.5 V, or 3.3 V domains) |
| Supply voltage (VCC) | 4 V to 5.5 V - compatible with standard 5-V TTL and mixed 3.3-V/5-V system rails when BIASV is decoupled |
| Operating temperature | –40°C to +85°C - qualified for industrial-grade embedded and telecom backplane environments |
| Input leakage current | ±5 µA max (at VCC = 5.5 V) - ensures low power consumption and stable enable control under static conditions |
| Thermal resistance (θJA) | 88°C/W (TSSOP-24 package) - defines maximum power dissipation limit (~150 mW at 85°C ambient) for continuous operation |
Pinout & Package
TSSOP-24 (PW) package: 7.8 mm × 4.4 mm × 1.2 mm body, 0.65 mm lead pitch, gull-wing leads, RoHS-compliant NiPdAu finish, MSL Level-1 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| ON (Pin 1) | Active-low enable input | Drives all 10 switches; low = A↔B connected, high = A isolated, B precharged to BIASV |
| A1–A10 (Pins 2–11) | Port A data inputs/outputs | Bidirectional TTL-compatible terminals; connect to upstream bus or controller side |
| GND (Pin 12) | Power ground reference | Common return for VCC, BIASV, and signal paths; must be low-impedance for noise control |
| VCC (Pin 13) | Positive supply rail | Powers internal switch circuitry and defines A-port logic thresholds (VIH/VIL) |
| B1–B10 (Pins 14–23) | Port B data inputs/outputs | Bidirectional terminals precharged to BIASV when ON = high; interface to hot-swappable modules |
| BIASV (Pin 24) | User-configurable bias voltage input | Sets precharge level for B ports; must be externally supplied and stable during insertion events |
Key Features
| Feature | Design Value |
|---|---|
| 10-bit bidirectional FET switch | Enables full-width data path isolation without direction control logic or bus transceivers |
| Precharged B-port outputs | Eliminates floating states during hot insertion by actively biasing B1–B10 to user-defined voltage |
| Low 5-Ω on-resistance | Minimizes IR drop and timing skew across all 10 channels, preserving signal edge fidelity |
| TTL-compatible control input | ON pin accepts standard 0.8 V / 2.0 V logic thresholds - interoperable with legacy 5-V microcontrollers |
| Mixed-voltage domain support | VCC and BIASV are independent supplies, enabling safe bridging between 5-V A-side and 1.8-/2.5-/3.3-V B-side systems |
Applications
| Hot-Swap Backplane Interface | Legacy Bus Isolation |
|---|---|
|
Use Scenario: Inserting/removing line cards into a powered telecom or server backplane without disrupting active data traffic. IC Role / Device Role / Timing Role: Bidirectional bus switch isolating card-local data lines (B-side) from shared backplane bus (A-side); ON controlled by card presence detection. Use Value: Precharged B ports prevent glitches and bus contention during insertion; 5-Ω ron maintains signal integrity at up to 100 MHz parallel bus rates. |
Use Scenario: Isolating obsolete 5-V parallel peripherals (e.g., ISA devices) from modern 3.3-V host controllers. IC Role / Device Role / Timing Role: Level-shifting and contention-free bus gate; A-side connects to 3.3-V controller, B-side to 5-V peripheral, BIASV set to 3.3 V. Use Value: Eliminates need for discrete level shifters or bus buffers; TTL-compatible ON input simplifies control logic integration. |
| Modular Test Equipment | Configurable I/O Expansion |
|
Use Scenario: Reconfiguring signal routing between DUT interfaces and measurement instruments in automated test systems. IC Role / Device Role / Timing Role: Low-latency, low-distortion 10-bit multiplexer; ON toggled under software control to route signals dynamically. Use Value: 0.25 ns tpd ensures sub-nanosecond timing alignment; precharge prevents false triggers during reconfiguration. |
Use Scenario: Adding flexible parallel I/O to FPGA-based embedded controllers where pin count or voltage compatibility varies per module. IC Role / Device Role / Timing Role: Voltage-agile bus extender; BIASV adjusted per module's logic family (1.8 V LVCMOS, 2.5 V, or 3.3 V), A-side tied to FPGA I/O bank. Use Value: Single IC replaces multiple discrete solutions; eliminates external pull-ups and reduces PCB area vs. discrete MOSFET arrays. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTD6800ADBQR | Includes bus-hold circuitry on B ports; higher ICC (100 µA typical); same ron, tpd, and package | Required where B ports must retain last state during disable (e.g., latch-sensitive interfaces); adds ~0.5 mA quiescent load | Select SN74CBTD6800ADBQR only if bus-hold functionality is explicitly needed; otherwise SN74CBT6800ADBQR offers lower power and simpler biasing. |
| SN74LVC1G3157DCKR | Single-pole double-throw (SPDT) analog switch; 5-V tolerant; 6 Ω ron; SC70-6 package; no BIASV or precharge | Only suitable for 1-bit signal routing; lacks multi-bit coordination, precharge, or hot-swap optimization | Use SN74LVC1G3157DCKR for low-pin-count analog/digital signal switching; not a functional replacement for 10-bit live-insertion use cases. |
Compared with SN74CBTD6800ADBQR and SN74LVC1G3157DCKR, the SN74CBT6800ADBQR uniquely delivers coordinated 10-bit precharge, zero-bus-contention disable behavior, and industrial temperature support in a space-efficient TSSOP-24 - making it the only direct solution for hot-swap backplane isolation.
Availability
SN74CBT6800ADBQR is available at Aetrix Electronics and suitable for hot-swap backplane interfaces, legacy bus isolation, modular test equipment, and configurable I/O expansion requiring stable component supply and long-term industrial availability.
Supply support for SN74CBT6800ADBQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in industrial, automotive, and communications markets.
The SN74CBT6800ADBQR belongs to TI's CBT (CrossBar Technology) logic family, engineered specifically for high-speed, low-distortion bus switching in live-insertion and hot-swap systems - prioritizing signal integrity, voltage flexibility, and robustness under dynamic load conditions.
FAQ
What is the function of the BIASV pin on the SN74CBT6800ADBQR?
The BIASV pin sets the precharge voltage applied to all B-port outputs (B1–B10) when the ON input is high (switch disabled). This prevents floating states during live insertion by actively biasing B ports to a defined voltage - typically matched to the downstream logic threshold (e.g., 1.8 V or 3.3 V). For the SN74CBT6800ADBQR, BIASV must be externally supplied within 1.3 V to VCC and remain stable during hot-plug events to ensure reliable noise suppression.
Can the SN74CBT6800ADBQR operate with VCC = 3.3 V?
No - the SN74CBT6800ADBQR is specified only for VCC = 4 V to 5.5 V per its recommended operating conditions. Operation below 4 V violates datasheet limits and risks unreliable switching, increased ron, and failure to meet VIH/VIL thresholds. However, BIASV may be set to 3.3 V (or lower) independently to interface with 3.3-V downstream logic, while VCC remains at 4.5 V or 5 V to ensure proper internal FET drive strength and timing performance of the SN74CBT6800ADBQR.
Is the SN74CBT6800ADBQR pin-compatible with other CBT-series 10-bit switches?
Yes - the SN74CBT6800ADBQR shares identical pinout and footprint with SN74CBT6800ADBR (SSOP), SN74CBT6800ADWR (SOIC), and SN74CBT6800ADGVR (TVSOP), as confirmed by TI's DB, DBQ, DGV, DW, and PW package drawings. All variants use the same 24-pin arrangement: ON, A1–A10, GND, VCC, B1–B10, BIASV. This enables direct package substitution without PCB redesign, provided thermal and mechanical constraints (e.g., TSSOP vs. SOIC height) are verified for the target assembly process.
What happens to the A-port pins when the SN74CBT6800ADBQR is disabled (ON = high)?
When ON = high, the internal FET switches open, electrically isolating A1–A10 from B1–B10. The A-port pins become high-impedance (Z-state) - neither driven nor precharged - and must be externally terminated if left unconnected to avoid noise coupling. Unlike the B ports, A ports have no internal bias network; their state depends entirely on external circuitry. This behavior is consistent across all operating conditions of the SN74CBT6800ADBQR and is documented in the FUNCTION TABLE.
Does the SN74CBT6800ADBQR support 5-V tolerant I/O on the B port?
No - the B ports of the SN74CBT6800ADBQR are not 5-V tolerant. Their voltage range is limited to 0 V to BIASV when enabled, and to BIASV ±0.5 V when disabled (per absolute maximum ratings). Exceeding BIASV on any B pin - including applying 5 V while BIASV = 3.3 V - risks damage. For 5-V tolerant operation, TI recommends the SN74CB3Q3245 or SN74CBT3245 families, which specify 5-V I/O tolerance independent of supply. The SN74CBT6800ADBQR requires BIASV to be set ≥ maximum expected B-port signal swing.
SN74CBT6800ADBQR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBT
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Bus Switch
- Circuit:
- 10 x 1:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
SN74CBT6800ADBQR FAQ
1.How can I place an order for SN74CBT6800ADBQR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBT6800ADBQR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBT6800ADBQR reliable?
The price and inventory of SN74CBT6800ADBQR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBT6800ADBQR is usually 5 days.
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5.How can I obtain technical support or documentation for SN74CBT6800ADBQR?
For technical support, including SN74CBT6800ADBQR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBT6800ADBQR requirements.
6.How does Aetrix verify that SN74CBT6800ADBQR is sourced from the original manufacturer or authorized distributors?
All SN74CBT6800ADBQR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBT6800ADBQR meets industry standards.
7.What is the process for return or replacement of SN74CBT6800ADBQR?
All SN74CBT6800ADBQR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBT6800ADBQR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBT6800ADBQR part is unused and in its original packaging.
Return procedure for SN74CBT6800ADBQR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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