Texas Instruments SN74CBTD3384CDBR
- Part No.:
- SN74CBTD3384CDBR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
SN74CBTD3384CDBR.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,000
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Product details
Overview
SN74CBTD3384CDBR from Texas Instruments is a 24-pin SSOP bidirectional FET bus switch IC with dual 5-bit configuration, 3 Ω typical ON-state resistance, −2 V undershoot protection on A/B ports, and integrated 5-V-to-3.3-V level shifting. It enables low-distortion signal gating in memory interleaving and bus isolation applications operating from 4.5 V to 5.5 V.
For engineers reviewing the SN74CBTD3384CDBR datasheet, SN74CBTD3384CDBR pinout, SN74CBTD3384CDBR application, or SN74CBTD3384CDBR equivalent, key selection criteria include its Ioff partial-power-down capability, 0.15 ns propagation delay, 5 pF OFF-state I/O capacitance, and support for 0–5 V signaling across 7 logic families (0.8 V to 5 V).
Technical Context
This device implements two independent 5-bit FET bus switches with separate OE controls (1OE, 2OE), enabling configurable 5-bit or 10-bit operation. Each switch uses low-threshold MOSFETs with active undershoot-protection circuitry that clamps A/B port voltages down to −2 V while maintaining OFF-state isolation.
The integrated VCC-series diode enables passive 5-V input to 3.3-V output level translation without external components. Control inputs accept TTL or 5-V/3.3-V CMOS logic, and Ioff ensures <10 µA backflow current during partial power-down, supporting hot-insertion and system-level power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures compatibility with standard 5-V supply rails and tolerance for line regulation drift. |
| ron (Typ) | 3 Ω - Minimizes voltage drop and power loss during bidirectional signal pass-through at ±128 mA max current. |
| tpd | 0.15 ns - Near-zero propagation delay preserves signal integrity in high-speed digital interconnects. |
| Cio(OFF) | 5 pF - Reduces capacitive loading and signal distortion when switch is disabled. |
| Undershoot Protection | −2 V on A/B ports - Prevents false triggering and latch-up during transient negative excursions in noisy environments. |
| Ioff | 10 µA - Blocks damaging back-current flow during partial power-down, enabling safe multi-rail system operation. |
| VI/O Range | 0 V to 5.5 V - Supports mixed-voltage signaling across 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic families. |
Pinout & Package
SN74CBTD3384CDBR uses a 24-pin SSOP (Shrink Small-Outline Package) with 0.65 mm pitch, 7.9 mm × 6.6 mm body size, and 1.2 mm max height per JEDEC MO-150.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE | Output-enable control inputs | Active-low enables respective 5-bit switch; tied to VCC via pullup for power-up high-impedance safety. |
| 1A1–1A5, 2A1–2A5 | Switch input/output port A | Bidirectional data terminals for first and second 5-bit buses; support 0–5 V signaling levels. |
| 1B1–1B5, 2B1–2B5 | Switch input/output port B | Electrically equivalent to A-side; connected to A-side when OE is low, isolated when OE is high. |
| VCC | Positive supply | Provides bias for internal FETs and undershoot protection circuitry; powers integrated level-shifting diode. |
| GND | Ground reference | Common return path for all I/O and supply currents; required for proper clamp diode and Ioff operation. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 5-V-to-3.3-V level shifter | Eliminates need for external level translators in mixed-voltage systems using 5-V drivers and 3.3-V receivers. |
| Undershoot protection (−2 V) | Prevents erroneous conduction and system instability during ESD or crosstalk-induced negative transients on data lines. |
| Ioff partial-power-down support | Enables safe insertion/removal of live cards or subsystems without disrupting powered sections of the backplane. |
| Bidirectional zero-delay switching | Preserves signal timing integrity in both directions without added latency or direction-control overhead. |
| Low 5 pF OFF-state capacitance | Minimizes signal reflection and crosstalk in high-frequency bus architectures such as memory channels. |
Applications
| Memory Interleaving | Bus Isolation |
|---|---|
|
Use Scenario: Separating two DRAM banks sharing a common address/data bus while enabling independent refresh cycles. IC Role / Device Role / Timing Role: Bidirectional bus switch isolating bank-select signals and data paths with sub-nanosecond delay. Use Value: Enables concurrent access to interleaved memory regions without timing skew or contention-induced corruption. |
Use Scenario: Electrically isolating legacy 5-V peripheral bus from modern 3.3-V microcontroller domain. IC Role / Device Role / Timing Role: Level-translating bus switch providing galvanic isolation and undershoot immunity between voltage domains. Use Value: Eliminates external level shifters and protection diodes while maintaining signal fidelity up to 100 MHz. |
| Low-Distortion Signal Gating | Hot-Swap Backplane Interface |
|
Use Scenario: Enabling/disabling analog sensor signals in precision data acquisition systems without introducing offset or noise. IC Role / Device Role / Timing Role: Low-capacitance, low-ron analog-capable switch routing differential or single-ended signals. Use Value: Maintains <1% THD across 0–5 V range due to linear RON and absence of CMOS threshold discontinuities. |
Use Scenario: Inserting/removing PCIe or CompactPCI modules into live backplanes without disrupting system operation. IC Role / Device Role / Timing Role: Ioff-enabled bus switch preventing backfeed current and ensuring high-Z state during power ramp-up/down. Use Value: Meets JESD78 Class II latch-up immunity (>100 mA) and supports hot-swap sequencing per PICMG standards. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384CDW | SOIC-24 package (10.75 mm × 15.7 mm); identical electrical specs and pinout; higher θJA (46°C/W vs 63°C/W). | Preferred for through-hole prototyping or legacy PCBs with SOIC footprints; less suitable for space-constrained layouts. | Select when board layout requires SOIC compatibility or thermal margin exceeds 63°C/W requirement. |
| SN74CBTD3384CPWR | TSSOP-24 package (6.95 mm × 8.3 mm); same VCC range, ron, and Ioff; lower Cio(OFF) (5 pF) but reduced creepage/clearance. | Better suited for ultra-dense consumer electronics; limited to ≤85°C ambient due to higher thermal resistance (88°C/W). | Choose for compact portable designs where footprint reduction outweighs thermal derating needs. |
Compared with SN74CBTD3384CDBR, the SOIC variant offers superior thermal performance for sustained high-current operation, while the TSSOP version delivers 30% smaller area at the cost of thermal headroom-making DBR optimal for balanced industrial density and reliability.
Availability
SN74CBTD3384CDBR is available at Aetrix Electronics and suitable for memory interleaving, bus isolation, and hot-swap backplane applications requiring stable component supply, long-term lifecycle continuity, and RoHS-compliant sourcing.
Supply support for SN74CBTD3384CDBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in high-reliability components.
The SN74CBTD3384CDBR belongs to TI's CBTD family of high-speed FET bus switches, designed specifically for low-latency, mixed-voltage digital interconnects in industrial, telecom, and computing infrastructure.
FAQ
What is the maximum undershoot voltage the SN74CBTD3384CDBR can tolerate on its A/B ports?
The SN74CBTD3384CDBR tolerates up to −2 V undershoot on both A and B ports under all operating conditions. This is achieved via active undershoot-protection circuitry that senses negative transients and forces the internal FETs into a guaranteed OFF state, preventing unintended conduction and protecting downstream logic. The specification is verified per test conditions in the datasheet with VCC = 5.5 V and switch OFF.
Does the SN74CBTD3384CDBR support true bidirectional signal flow without direction control pins?
Yes, the SN74CBTD3384CDBR supports fully bidirectional signal flow with no direction control required. Its FET-based architecture provides symmetrical conduction between A and B ports when enabled by 1OE or 2OE. Signal polarity, amplitude, and timing are preserved in both directions, making it ideal for data buses, clock distribution, and analog signal routing where direction reversal occurs dynamically.
How does the integrated level-shifting diode in the SN74CBTD3384CDBR function?
The SN74CBTD3384CDBR integrates a diode in series with VCC to enable passive 5-V-to-3.3-V level shifting: when a 5-V signal drives an A-port pin, the diode drops ~1.7 V (typical), delivering ~3.3 V to the B port. This eliminates external components while maintaining rail-to-rail signal swing. The effect is most consistent at moderate frequencies; high-edge-rate signals may exhibit reduced translation due to parasitic capacitance.
What is the purpose of the Ioff feature in the SN74CBTD3384CDBR, and how is it implemented?
The Ioff feature in the SN74CBTD3384CDBR limits backflow current to ≤10 µA when VCC = 0 V and I/O pins are biased to 0–5.5 V, preventing damage during partial power-down. It is implemented via internal transistor biasing that disables all channel conduction paths while maintaining isolation. This enables safe hot-swap operation and multi-rail power sequencing without external isolation circuitry.
Can the SN74CBTD3384CDBR be used for analog signal switching, and what are its limitations?
Yes, the SN74CBTD3384CDBR supports analog signal switching due to its low 3 Ω ron, 5 pF Cio(OFF), and rail-to-rail VI/O range (0–5.5 V). Limitations include no guaranteed monotonicity above 10 MHz, potential THD increase near voltage rails due to FET nonlinearity, and absence of specified analog bandwidth or settling time-making it suitable for DC–10 MHz audio, sensor, and control signals but not RF or precision DAC/ADC interfaces.
SN74CBTD3384CDBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTD
- Package/Case:
- 24-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
SN74CBTD3384CDBR FAQ
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7.What is the process for return or replacement of SN74CBTD3384CDBR?
All SN74CBTD3384CDBR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTD3384CDBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTD3384CDBR part is unused and in its original packaging.
Return procedure for SN74CBTD3384CDBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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