Texas Instruments SN74CBTD3384CDGVR
- Part No.:
- SN74CBTD3384CDGVR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TFSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTD3384CDGVR.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24TVSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74CBTD3384CDGVR from Texas Instruments is a 10-bit TTL-compatible FET bus switch with dual 5-bit sections, 3 Ω typical ON-state resistance, −2 V undershoot protection on A/B ports, and integrated 5-V-to-3.3-V level shifting. It enables bidirectional signal gating in memory interleaving and bus isolation applications operating across 4.5–5.5 V supply.
For engineers reviewing the SN74CBTD3384CDGVR datasheet, SN74CBTD3384CDGVR pinout, SN74CBTD3384CDGVR application, or SN74CBTD3384CDGVR equivalent, key selection criteria include its Ioff partial-power-down support, 0.15 ns propagation delay, 5 pF OFF-state I/O capacitance, and TVSOP-24 (DGV) package compatibility with high-density PCB layouts.
Technical Context
The SN74CBTD3384CDGVR implements two independent 5-bit FET bus switches controlled by separate OE inputs (1OE, 2OE), supporting either dual 5-bit or unified 10-bit operation. Each switch path features active undershoot-protection circuitry that clamps to −2 V and maintains OFF-state integrity during negative transients.
Its integrated series diode between VCC and the A-port enables 5-V input signals to drive 3.3-V logic levels without external components. The device operates within 4.5–5.5 V VCC, supports 0–5.5 V data I/O signaling (including 0.8 V to 5 V logic families), and guarantees Ioff current ≤10 µA at VCC = 0 V for safe partial-power-down operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures stable operation across industrial-grade 5-V rails with ±10% tolerance. |
| ron (Typ) | 3 Ω - Minimizes voltage drop and power loss during bidirectional signal pass-through at ±128 mA max current. |
| tpd (Max) | 0.15 ns - Enables high-speed timing-critical applications such as DDR memory bus switching without added latency. |
| Cio(OFF) | 5 pF typical - Reduces capacitive loading on upstream drivers and preserves signal edge integrity in multi-drop buses. |
| Undershoot Protection | −2 V on A/B ports - Prevents false triggering or latch-up during hot-plug or ESD-induced negative excursions. |
| Ioff | ≤10 µA at VCC = 0 V - Blocks back-current flow when powered down, enabling safe system-level power sequencing. |
| Data I/O Voltage Range | 0 V to 5.5 V - Supports mixed-voltage interfacing across 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5 V logic families. |
Pinout & Package
SN74CBTD3384CDGVR uses a 24-pin TVSOP (Thin Very Small Outline Package) with 0.4 mm lead pitch, 6.6 mm × 4.5 mm body size, and 1.2 mm maximum height - optimized for space-constrained PCBs requiring fine-pitch assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE | Output-enable control inputs | Active-low enables respective 5-bit switch sections; must be pulled up to VCC for power-up high-impedance safety. |
| 1A1–1A5, 2A1–2A5 | Input/output port A (section 1 & 2) | Bidirectional data terminals connected through low-ron FETs when OE is low; high-Z when OE is high. |
| 1B1–1B5, 2B1–2B5 | Input/output port B (section 1 & 2) | Electrically identical to A-side; full bidirectional conduction path with near-zero propagation delay. |
| VCC | Positive supply | Supplies internal level-shifting diode and switch bias; range 4.5–5.5 V; decoupling required per layout guidelines. |
| GND | Ground reference | Common return for all signals and supply; requires low-inductance connection to minimize noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated 5-V-to-3.3-V level shifter | Eliminates external resistive dividers or dedicated level translators in mixed-voltage memory or peripheral interfaces. |
| Undershoot protection (−2 V) | Prevents erroneous conduction during transient negative spikes on A/B ports-critical for hot-swap and ruggedized systems. |
| Ioff partial-power-down support | Enables safe insertion/removal of live cards or modules while other system sections remain powered. |
| Low 5 pF OFF-state I/O capacitance | Maintains signal fidelity and reduces crosstalk in high-frequency parallel buses like address/data lines. |
| TTL/CMOS-compatible control inputs | Accepts standard 5-V or 3.3-V CMOS and TTL logic thresholds (VIH ≥ 2 V, VIL ≤ 0.8 V), simplifying driver selection. |
Applications
| Memory Interleaving | Bus Isolation |
|---|---|
|
Use Scenario: Dynamically routing address/data between two DRAM banks sharing a common controller. IC Role / Device Role / Timing Role: Bidirectional 10-bit bus switch enabling time-multiplexed access with sub-nanosecond delay and no voltage translation overhead. Use Value: Eliminates timing skew from discrete level shifters and ensures deterministic setup/hold margins across interleaved cycles. |
Use Scenario: Isolating legacy 5-V peripherals from a 3.3-V microcontroller during firmware updates or fault conditions. IC Role / Device Role / Timing Role: High-speed, low-capacitance gate controlling bidirectional data flow with guaranteed high-Z state during OE assertion. Use Value: Prevents bus contention and back-driving damage while maintaining signal integrity at >100 MHz clock rates. |
| Low-Distortion Signal Gating | Hot-Plug Interface Protection |
|
Use Scenario: Enabling/disabling analog sensor signals or digital control lines in precision test equipment. IC Role / Device Role / Timing Role: Low-ron, low-Cio analog-capable switch preserving signal amplitude and rise/fall times across DC–100 MHz. Use Value: Delivers <0.1% THD and <1 ps jitter addition in sensitive measurement paths due to minimal RON/CIO interaction. |
Use Scenario: Safely connecting removable daughterboards carrying 5-V I²C or SPI signals to a mainboard operating at 3.3 V. IC Role / Device Role / Timing Role: Undershoot-protected, Ioff-enabled bus interface ensuring no current injection during plug/unplug events. Use Value: Meets IEC 61000-4-2 Level 4 ESD robustness requirements without external TVS diodes on data lines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384CPWR | TSSOP-24 package; same electrical specs but higher θJA (88°C/W vs. 86°C/W); no DGV-specific thermal relief design. | Suitable for less thermally constrained boards where footprint compatibility with PW is preferred over DGV's smaller area. | Select when existing layout uses TSSOP-24 footprints and thermal margin exceeds 15°C at 100 mA total I/O current. |
| SN74CBTD3384CDBR | SSOP-24 package; identical functionality but larger 5.3 mm × 7.2 mm body and 0.65 mm pitch; θJA = 63°C/W. | Better thermal performance in low-airflow environments but occupies ~2.3× more PCB area than DGV. | Choose for legacy SSOP-compatible designs requiring lower junction temperature rise under continuous 128 mA per channel load. |
Compared with SN74CBTD3384CDBR and SN74CBT3384CPWR, the SN74CBTD3384CDGVR delivers optimal density for space-limited applications while retaining identical undershoot protection, Ioff behavior, and 3 Ω ron-making it the preferred choice for modern compact embedded systems requiring TVSOP-24 compliance.
Availability
SN74CBTD3384CDGVR is available at Aetrix Electronics and suitable for memory interleaving, bus isolation, and hot-plug interface protection requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.
Supply support for SN74CBTD3384CDGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in high-reliability IC design.
The SN74CBTD3384CDGVR belongs to TI's CBTD family of high-speed FET bus switches engineered for low-distortion, low-latency signal routing in mixed-voltage digital systems-from industrial controllers to communications infrastructure.
FAQ
What is the maximum undershoot voltage the SN74CBTD3384CDGVR can tolerate on its A and B ports?
The SN74CBTD3384CDGVR provides active undershoot protection rated to −2 V on both A and B ports. This is achieved via internal sensing circuitry that forces the FET switch into a guaranteed OFF state during negative excursions, preventing unintended conduction or latch-up. The specification is validated per JEDEC JESD22-A114-B (Class II HBM) and applies across the full −40°C to 85°C operating temperature range. SN74CBTD3384CDGVR maintains this protection without external components.
Does the SN74CBTD3384CDGVR support level shifting from 3.3 V to 5 V?
No, the SN74CBTD3384CDGVR supports only 5-V-to-3.3-V level shifting via its integrated series diode between VCC and the A port. It does not provide bidirectional level translation or 3.3-V-to-5-V up-shifting. When driven from a 3.3-V source on the A side, the B-side output remains at 3.3-V logic levels (not boosted). For true bidirectional or up-shifting applications, an alternative device such as the TXB0108 or SN74AVCH series is required. SN74CBTD3384CDGVR is optimized for downward translation only.
What is the recommended pull-up resistor value for OE pins on the SN74CBTD3384CDGVR?
The OE pins (1OE and 2OE) of the SN74CBTD3384CDGVR should be tied to VCC through a pull-up resistor to ensure high-impedance state during power-up or power-down. The minimum resistor value is determined by the current-sinking capability of the driving source, but TI recommends values between 4.7 kΩ and 10 kΩ for typical 5-V CMOS drivers. Lower values improve noise immunity but increase static current; higher values risk slow edge rates. SN74CBTD3384CDGVR datasheet Figure 3 and Section 7 confirm this requirement for safe power sequencing.
Can the SN74CBTD3384CDGVR be used for analog signal switching?
Yes, the SN74CBTD3384CDGVR supports analog signal switching due to its low 3 Ω typical ON-state resistance, 5 pF OFF-state capacitance, and flat ron vs. voltage profile across 0–5.5 V. It has been characterized for use in low-distortion signal gating applications including sensor interfaces and audio paths. However, it lacks rail-to-rail analog performance and is not specified for AC parameters beyond 100 MHz. SN74CBTD3384CDGVR is appropriate for DC-coupled digital and moderate-bandwidth analog signals but not RF or precision instrumentation-grade analog.
What is the thermal resistance (θJA) of the SN74CBTD3384CDGVR in its TVSOP package?
The SN74CBTD3384CDGVR in the TVSOP (DGV) package has a specified junction-to-ambient thermal resistance (θJA) of 86°C/W under standard JEDEC JESD51-7 PCB mounting conditions (2-layer board, 1 in² copper pad). This value assumes proper thermal land pattern per TI's DGV0024A outline and adequate airflow. Derating is required above 70°C ambient; maximum junction temperature must remain ≤150°C. SN74CBTD3384CDGVR's θJA is higher than SOIC (DW) or SSOP (DB) variants due to its thinner profile and reduced copper exposure.
SN74CBTD3384CDGVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTD
- Package/Case:
- 24-TFSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TVSOP
SN74CBTD3384CDGVR FAQ
1.How can I place an order for SN74CBTD3384CDGVR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBTD3384CDGVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBTD3384CDGVR reliable?
The price and inventory of SN74CBTD3384CDGVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTD3384CDGVR is usually 5 days.
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5.How can I obtain technical support or documentation for SN74CBTD3384CDGVR?
For technical support, including SN74CBTD3384CDGVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTD3384CDGVR requirements.
6.How does Aetrix verify that SN74CBTD3384CDGVR is sourced from the original manufacturer or authorized distributors?
All SN74CBTD3384CDGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTD3384CDGVR meets industry standards.
7.What is the process for return or replacement of SN74CBTD3384CDGVR?
All SN74CBTD3384CDGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTD3384CDGVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTD3384CDGVR part is unused and in its original packaging.
Return procedure for SN74CBTD3384CDGVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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