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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74CBTLV1G125C6

Name: SN74CBTLV1G125C6
Brand: Texas Instruments
SKU: SN74CBTLV1G125C6
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74CBTLV1G125C6

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: -

Datasheet:: SN74CBTLV1G125C6.pdf

Description:: SN74CBTLV1G125DCK6

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Product details

Overview

SN74CBTLV1G125C6 from Texas Instruments is a low-voltage single FET bus switch with 5-Ω on-state resistance, rail-to-rail signal switching, and I_off support for partial-power-down operation. It functions as a bidirectional, OE-controlled analog switch in high-speed data paths, enabling/disabling signal flow between A and B ports in compact logic-level interfaces.

For engineers reviewing the SN74CBTLV1G125C6 datasheet, SN74CBTLV1G125C6 pinout, SN74CBTLV1G125C6 application, or SN74CBTLV1G125C6 equivalent, this device is selected for low-latency, low-capacitance signal routing in space-constrained 2.3–3.6 V systems requiring power-aware isolation and minimal propagation delay (0.15 ns typical).

Technical Context

The SN74CBTLV1G125C6 implements a single-channel, NMOS-based transmission gate architecture with no internal level-shifting circuitry. Its control logic is positive-true: OE low enables conduction (A ↔ B), OE high places both ports in high-impedance state.

It operates across 2.3 V to 3.6 V supply range with guaranteed performance at 2.5 V and 3.3 V. The device supports rail-to-rail analog/digital signal pass-through and maintains <7 pF off-state capacitance (C_io(OFF)) to minimize loading on high-speed buses.

Key Specifications

Parameter	Value and Actual Design Meaning
On-state resistance (r_on)	5 Ω typical at V_CC = 3 V - ensures minimal voltage drop and signal distortion for ≤64 mA channel current.
Propagation delay (t_pd)	0.15 ns typical at V_CC = 3.3 V - enables sub-nanosecond timing integrity in DDR, PCIe, or USB signal routing.
Off-state capacitance (C_io(OFF))	7 pF maximum at V_O = 3 V - reduces crosstalk and preserves signal edge rate in dense PCB layouts.
I_off leakage	10 µA maximum at V_CC = 0 V - prevents backflow current during partial power-down, protecting powered subsystems.
Supply voltage range	2.3 V to 3.6 V - compatible with modern low-voltage I/O standards including LVTTL, LVCMOS, and sub-3.3 V ASIC interfaces.
Input capacitance (C_i)	2.5 pF typical - minimizes driver loading and simplifies termination design for high-frequency control signals.
Enable/disable time (t_en/t_dis)	1–4 ns typical - supports fast dynamic bus arbitration without glitches or metastability.

Pinout & Package

SOT-23 (DBV) 5-pin plastic package, 1.45 mm max height, JEDEC MO-178 compliant, footprint-compatible with industry-standard SOT-23 land patterns.

Pin/Terminal	Circuit Role	Design Meaning
1 - OE	Output-enable control input	Active-low logic signal; must be pulled high via external resistor during power-up/down to guarantee high-Z state.
2 - GND	Ground reference	Primary return path for switch current and control logic; requires low-inductance connection to system ground plane.
3 - A	Data port A terminal	Bidirectional signal node; connects to upstream source (e.g., processor GPIO or memory controller).
4 - B	Data port B terminal	Bidirectional signal node; connects to downstream load (e.g., peripheral interface or level translator).
5 - V_CC	Power supply	Supplies bias for internal FET gate drive; must be decoupled locally with ≥0.1 µF ceramic capacitor.

Key Features

Feature	Design Value
5-Ω low on-resistance	Preserves signal integrity for high-speed digital and analog signals up to 200 MHz without significant attenuation.
I_off partial-power-down protection	Enables safe integration into mixed-voltage systems where one side may be unpowered while the other remains active.
Rail-to-rail signal handling	Supports full-swing signals from GND to V_CC, eliminating need for external level shifters in same-supply domain interconnects.
Sub-0.25 ns propagation delay	Maintains timing margins in high-frequency clock distribution, address/data multiplexing, and hot-swap control paths.
7 pF off-state capacitance	Reduces capacitive loading on shared buses, improving rise/fall times and reducing EMI coupling in multi-drop topologies.

Applications

PCIe Gen1/Gen2 Reference Clock Switching	USB 2.0 Data Line Isolation
Use Scenario: Selecting between two reference clock sources for FPGA or SoC PLL input during boot or reconfiguration. IC Role / Device Role / Timing Role: Bidirectional, low-latency clock path selector with zero added jitter and no duty-cycle distortion. Use Value: Enables glitch-free clock source switchover while maintaining <0.15 ns skew and preserving phase alignment critical for SerDes lock stability.	Use Scenario: Isolating USB D+/D− lines during device insertion/removal to prevent bus contention and host enumeration errors. IC Role / Device Role / Timing Role: High-speed analog switch controlled by microcontroller GPIO to gate USB data traffic before VBUS presence detection. Use Value: Eliminates need for mechanical switches or complex USB transceivers; supports hot-plug compliance with <4 ns enable/disable response.
Low-Voltage Memory Address Multiplexing	FPGA I/O Expansion Bus Gating
Use Scenario: Sharing a single address/data bus between two low-power SRAM banks in battery-operated IoT nodes. IC Role / Device Role / Timing Role: Low-resistance, low-capacitance bus switch enabling time-multiplexed access without signal degradation. Use Value: Reduces component count vs. dual-port RAM; maintains 100+ MHz address strobe timing with <5 Ω r_on and <7 pF C_io(OFF).	Use Scenario: Dynamically enabling/disabling I/O expansion headers on industrial FPGA carrier boards based on peripheral presence detection. IC Role / Device Role / Timing Role: Signal isolation gate for parallel GPIO, SPI, or I²C expansion buses under firmware control. Use Value: Prevents floating inputs and leakage paths when peripherals are absent; supports seamless plug-and-play with no layout changes required.

PCIe Gen1/Gen2 Reference Clock Switching

USB 2.0 Data Line Isolation

Use Scenario: Selecting between two reference clock sources for FPGA or SoC PLL input during boot or reconfiguration.

IC Role / Device Role / Timing Role: Bidirectional, low-latency clock path selector with zero added jitter and no duty-cycle distortion.

Use Value: Enables glitch-free clock source switchover while maintaining <0.15 ns skew and preserving phase alignment critical for SerDes lock stability.

Use Scenario: Isolating USB D+/D− lines during device insertion/removal to prevent bus contention and host enumeration errors.

IC Role / Device Role / Timing Role: High-speed analog switch controlled by microcontroller GPIO to gate USB data traffic before VBUS presence detection.

Use Value: Eliminates need for mechanical switches or complex USB transceivers; supports hot-plug compliance with <4 ns enable/disable response.

Low-Voltage Memory Address Multiplexing

FPGA I/O Expansion Bus Gating

Use Scenario: Sharing a single address/data bus between two low-power SRAM banks in battery-operated IoT nodes.

IC Role / Device Role / Timing Role: Low-resistance, low-capacitance bus switch enabling time-multiplexed access without signal degradation.

Use Value: Reduces component count vs. dual-port RAM; maintains 100+ MHz address strobe timing with <5 Ω r_on and <7 pF C_io(OFF).

Use Scenario: Dynamically enabling/disabling I/O expansion headers on industrial FPGA carrier boards based on peripheral presence detection.

IC Role / Device Role / Timing Role: Signal isolation gate for parallel GPIO, SPI, or I²C expansion buses under firmware control.

Use Value: Prevents floating inputs and leakage paths when peripherals are absent; supports seamless plug-and-play with no layout changes required.

Equivalent & Alternatives

The following parts are listed as comparable options for similar bus switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74CB3Q1G125DBVR	Lower r_on (2.5 Ω typ), higher ICC (20 µA), supports 1.65–3.6 V range	Better for ultra-low-loss signal paths but consumes more quiescent current	Select when minimizing voltage drop at >100 mA loads outweighs static power budget constraints.
NC7SZ125P5X	Higher r_on (12 Ω typ), no I_off support, 1.65–5.5 V range	Lacks partial-power-down protection; suitable only for fully powered systems	Choose for cost-sensitive designs where full-system power cycling is guaranteed and rail-to-rail switching is not required.

Compared with SN74CBTLV1G125C6, SN74CB3Q1G125DBVR delivers lower on-resistance at the expense of higher supply current and tighter voltage margin, while NC7SZ125P5X offers broader voltage compatibility but sacrifices I_off safety and signal fidelity-making SN74CBTLV1G125C6 optimal for robust, low-power, mixed-domain isolation.

Availability

SN74CBTLV1G125C6 is available at Aetrix Electronics and suitable for PCIe clock routing, USB 2.0 isolation, and FPGA I/O expansion applications requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant packaging.

Supply support for SN74CBTLV1G125C6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with emphasis on reliability, precision, and energy efficiency across industrial, automotive, and communications markets.

The SN74CBTLV1G125C6 belongs to TI's CBTLV (low-voltage FET bus switch) product line, engineered specifically for high-speed, low-power signal gating in portable, space-constrained, and mixed-supply electronic systems.

FAQ

What is the recommended pull-up resistor value for the OE pin of SN74CBTLV1G125C6 during power-up?

The minimum pull-up resistor value for the OE pin of SN74CBTLV1G125C6 is determined by the current-sinking capability of the driving source. TI specifies that OE must be tied to V_CC through a pull-up resistor to ensure high-impedance state during power transitions. For standard CMOS drivers with 8 mA sink capability, a 10 kΩ resistor is commonly used; values between 4.7 kΩ and 100 kΩ maintain noise immunity while limiting current draw. Always verify against the actual driver's I_OL rating per the SN74CBTLV1G125C6 datasheet Section 7.3.

Does SN74CBTLV1G125C6 support bidirectional signal flow between A and B ports?

Yes, SN74CBTLV1G125C6 supports fully bidirectional signal flow: when OE is low, the internal FET switch creates a symmetric, low-resistance path between A and B terminals, allowing signals to pass in either direction without polarity inversion or level translation. This behavior is confirmed in the functional table and simplified schematic of the SN74CBTLV1G125C6 datasheet, and applies across the full 2.3–3.6 V supply range with rail-to-rail voltage handling.

Can SN74CBTLV1G125C6 be used in 1.8 V systems?

No, SN74CBTLV1G125C6 is not rated for 1.8 V operation. Its recommended operating supply voltage range is 2.3 V to 3.6 V, with absolute maximum V_CC of 4.6 V and minimum functional V_CC of 2.3 V. At 1.8 V, the internal FET gate drive is insufficient to achieve specified r_on or switching speed; functionality is not guaranteed. For 1.8 V systems, consider TI's SN74CBTLV3125 or ON Semiconductor's NL17SZ125 as alternatives explicitly characterized down to 1.65 V.

What is the thermal resistance (θ_JA) of SN74CBTLV1G125C6 in the DBV package?

The junction-to-ambient thermal resistance (θ_JA) of SN74CBTLV1G125C6 in the SOT-23 (DBV) package is 206 °C/W, as specified in the Absolute Maximum Ratings table of the official SN74CBTLV1G125C6 datasheet. This value assumes standard JEDEC test conditions (single-layer board, 1 in² copper pad). Actual thermal performance improves with enhanced PCB copper area, thermal vias, or airflow, but derating is required above 85°C ambient per TI's recommended operating conditions.

Is SN74CBTLV1G125C6 pin-compatible with SN74CBTLV1G125DBVR or SN74CBTLV1G125DCKR?

Yes, SN74CBTLV1G125C6 shares identical pinout (OE, GND, A, B, V_CC) and function with SN74CBTLV1G125DBVR (SOT-23) and SN74CBTLV1G125DCKR (SC-70); all three variants use the same logic diagram, functional table, and electrical specifications. However, physical package dimensions differ: DBV is 2.92 × 1.62 mm, DCK is 2.0 × 1.25 mm. Layout adaptation is required when substituting between packages, though schematic connectivity remains unchanged.

SN74CBTLV1G125C6 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74CBTLV

Package/Case:: -

Packaging:: Bulk

Product Status:: Obsolete

Type:: Bus Switch

Circuit:: 1 x 1:1

Independent Circuits:: 1

Current - Output High, Low:: -

Voltage Supply Source:: Single Supply

Voltage - Supply:: 2.3V ~ 3.6V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: -

SN74CBTLV1G125C6 FAQ

1.How can I place an order for SN74CBTLV1G125C6 through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74CBTLV1G125C6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74CBTLV1G125C6 reliable?

The price and inventory of SN74CBTLV1G125C6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTLV1G125C6 is usually 5 days.

3.What payment methods are accepted for SN74CBTLV1G125C6?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74CBTLV1G125C6 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74CBTLV1G125C6?

SN74CBTLV1G125C6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74CBTLV1G125C6 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74CBTLV1G125C6?

For technical support, including SN74CBTLV1G125C6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV1G125C6 requirements.

6.How does Aetrix verify that SN74CBTLV1G125C6 is sourced from the original manufacturer or authorized distributors?

All SN74CBTLV1G125C6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV1G125C6 meets industry standards.

7.What is the process for return or replacement of SN74CBTLV1G125C6?

All SN74CBTLV1G125C6 units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV1G125C6, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74CBTLV1G125C6 part is unused and in its original packaging.

Return procedure for SN74CBTLV1G125C6:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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