Texas Instruments SN74CBTLV3125DGVR
- Part No.:
- SN74CBTLV3125DGVR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-TFSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTLV3125DGVR.pdf
- Description:
- IC BUS SWITCH 1 X 1:1 14TVSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,230
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Product details
Overview
SN74CBTLV3125DGVR from Texas Instruments is a low-voltage quadruple FET bus switch with independent 1A/1B–4A/4B bidirectional channels, 5 Ω on-state resistance at 3.3 V, rail-to-rail signal switching, and Ioff partial-power-down protection. It operates from 2.3 V to 3.6 V and supports hot-swap isolation in datacenter interconnects and protocol routing.
For engineers reviewing the SN74CBTLV3125DGVR datasheet, SN74CBTLV3125DGVR pinout, SN74CBTLV3125DGVR application, or SN74CBTLV3125DGVR equivalent, this page delivers verified electrical specs, TVSOP-14 package details, OE-controlled channel enable/disable timing, and real-world isolation use cases for JTAG/SPI signal routing without power sequencing.
Technical Context
The SN74CBTLV3125DGVR implements four independent NMOS pass-gate switches, each controlled by a dedicated active-high output-enable (OE) input. Its Ioff specification limits leakage to ≤10 µA when VCC = 0 V and ports are biased up to 3.6 V, enabling true isolation during system power-down.
Switching performance is characterized by 0.25 ns typical propagation delay (tpd) and 4.4 ns max enable time (ten) at 3.3 V, with on-resistance varying from 5 Ω (VI = 0 V, II = 64 mA) to 15 Ω (VI = 2.4 V, II = 15 mA). Latch-up immunity exceeds 100 mA per JESD78 Class II.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.3 V to 3.6 V - Enables direct interface with 2.5 V and 3.3 V logic domains without level translation. |
| On-State Resistance | 5 Ω typical at 3.3 V, 64 mA - Minimizes voltage drop and signal distortion across high-speed data paths. |
| Ioff Leakage | ≤10 µA at VCC = 0 V - Prevents backflow current during partial power-down, critical for hot-swap safety. |
| Propagation Delay | 0.25 ns typical at 3.3 V - Supports >1 GHz signal integrity in protocol isolation applications. |
| Enable Time (ten) | 4.4 ns max at 3.3 V - Ensures fast, deterministic channel activation for dynamic bus routing. |
| ESD Rating | ±2000 V HBM - Meets industrial handling requirements without additional protection circuitry. |
| Operating Temperature | −40 °C to +85 °C - Validated for enterprise computing and wired networking ambient conditions. |
Pinout & Package
SN74CBTLV3125DGVR uses the TVSOP-14 (DGV) package: 3.60 mm × 4.40 mm body, 0.65 mm lead pitch, exposed pad optional, RoHS-compliant NiPdAu finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE, 3OE, 4OE | Active-high enable input | Each controls one channel; high = high-impedance disconnect, low = bidirectional conduction. |
| 1A, 2A, 3A, 4A | Data I/O port A | One side of each FET switch; supports rail-to-rail voltage swing (0 V to VCC). |
| 1B, 2B, 3B, 4B | Data I/O port B | Other side of each FET switch; electrically identical to port A, fully bidirectional. |
| VCC | Power supply | Single 2.3–3.6 V supply; powers internal bias and switch control logic. |
| GND | Ground reference | Return path for all signals and supply current; must be low-impedance for noise control. |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail switching | Supports full 0 V to VCC signal swing on both A and B ports-no clamping or level-shifting needed. |
| Ioff partial-power-down | Guarantees ≤10 µA leakage when unpowered, enabling safe live insertion into powered-backplane systems. |
| 5 Ω low on-resistance | Reduces insertion loss and maintains signal edge fidelity for high-speed digital buses up to 500 Mbps. |
| Independent channel control | Four separate OE inputs allow granular, asynchronous enable/disable of individual data paths. |
| Latch-up immunity | Exceeds 100 mA per JESD78 Class II-ensures robust operation in noisy industrial environments. |
Applications
| Protocol Isolation | Hot-Swap Backplane |
|---|---|
|
Use Scenario: Isolating JTAG debug, SPI flash, or GPIO signals between processor and peripherals in shared bus architectures. IC Role / Device Role / Timing Role: Bidirectional signal gate with sub-nanosecond propagation delay and independent OE control per channel. Use Value: Eliminates need for external level shifters or sequenced power rails-enables zero-latency protocol routing. |
Use Scenario: Enabling live insertion/removal of line cards in enterprise switches or storage controllers without system reset. IC Role / Device Role / Timing Role: Power-domain isolator using Ioff to block backfeed current when card VCC is off. Use Value: Prevents damage to upstream logic during hot-plug events; meets IEC 61000-4-2 ESD immunity requirements. |
| Server Memory Interconnect | Industrial I/O Expansion |
|
Use Scenario: Routing SMBus, PMBus, or sideband signals between baseboard management controller (BMC) and DIMM modules. IC Role / Device Role / Timing Role: Low-capacitance (7 pF OFF), low-Ron bus switch preserving signal rise/fall times. Use Value: Maintains timing margins for 100 kHz–400 kHz control buses while adding no measurable skew. |
Use Scenario: Multiplexing sensor inputs or actuator outputs across multiple fieldbus nodes in building automation PLCs. IC Role / Device Role / Timing Role: Fault-tolerant signal router with latch-up immunity and −40 °C to +85 °C operation. Use Value: Reduces component count vs. discrete MOSFET solutions; simplifies PCB layout with single-chip quad routing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3245DGVR | Octal (8-channel) configuration, same 5 Ω Ron, identical TVSOP-20 package; higher channel density but larger footprint. | Used where board space allows wider bus expansion (e.g., PCIe sideband routing), not direct replacement for quad-channel layouts. | Select when consolidating multiple SN74CBTLV3125DGVR functions onto one IC to reduce BOM count and routing complexity. |
| SN74LVC1G3157DCKR | Single-channel SPDT analog switch, 10 Ω Ron, SC70-6 package; lower integration, higher Ron, no Ioff spec. | Suitable for low-pin-count microcontroller GPIO expansion, not for multi-lane protocol isolation requiring simultaneous channel control. | Choose only for cost-sensitive, low-channel-count designs where Ioff and rail-to-rail performance are non-critical. |
Compared with SN74CBTLV3125DGVR, SN74CBTLV3245DGVR offers double channel count in a larger package for bus-wide routing, while SN74LVC1G3157DCKR provides minimal footprint at the expense of isolation capability and multi-channel coordination.
Availability
SN74CBTLV3125DGVR is available at Aetrix Electronics and suitable for datacenter interconnects, enterprise server backplanes, and industrial I/O expansion requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for SN74CBTLV3125DGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader designing analog ICs, embedded processors, and connectivity solutions for industrial, automotive, and communications markets.
The SN74CBTLV3125DGVR belongs to TI's CBTLV low-voltage bus switch family, engineered specifically for high-speed, low-distortion signal routing in power-aware systems with hot-swap and partial-power-down requirements.
FAQ
What is the maximum operating temperature for SN74CBTLV3125DGVR?
The SN74CBTLV3125DGVR is rated for operation from −40 °C to +85 °C ambient temperature. This range applies specifically to the TVSOP-14 (DGV) package variant and is validated per TI's recommended operating conditions in the SCDS037K datasheet. Operation beyond +85 °C is not specified or guaranteed.
Does SN74CBTLV3125DGVR support 1.8 V logic interfaces?
Yes, SN74CBTLV3125DGVR supports 1.8 V-compatible control logic: its VIL is 0.7 V (max) at VCC = 2.3–2.7 V and 0.8 V (max) at VCC = 2.7–3.6 V, ensuring reliable low-level recognition from 1.8 V drivers. Signal I/O ports also accept 0–VCC swings, accommodating 1.8 V data levels when VCC ≥ 1.8 V.
How does the Ioff feature function in SN74CBTLV3125DGVR?
In SN74CBTLV3125DGVR, Ioff limits current flow to ≤10 µA when VCC = 0 V and any I/O port is biased between 0 V and 3.6 V. This prevents damaging backfeed current during partial power-down, enabling safe hot-swap operation. The feature is inherent to the device's FET structure and requires no external circuitry.
What is the typical on-state resistance of SN74CBTLV3125DGVR at 3.3 V?
The typical on-state resistance (Ron) of SN74CBTLV3125DGVR is 5 Ω at VCC = 3.3 V, measured with VI = 0 V and II = 64 mA. At VI = 2.4 V and II = 15 mA, Ron rises to 10–15 Ω. These values are specified for the DGV package and directly impact voltage drop and signal integrity in high-current data paths.
Can SN74CBTLV3125DGVR be used with 5 V systems?
No, SN74CBTLV3125DGVR is not rated for 5 V operation. Its absolute maximum supply voltage is 4.6 V, and recommended operating range is strictly 2.3 V to 3.6 V. Applying 5 V to VCC or I/O ports violates absolute maximum ratings and risks permanent damage. For 5 V systems, consider TI's SN74CBT3245 or similar 5 V-tolerant families.
SN74CBTLV3125DGVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 14-TFSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 1 x 1:1
- Independent Circuits:
- 4
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TVSOP
SN74CBTLV3125DGVR FAQ
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6.How does Aetrix verify that SN74CBTLV3125DGVR is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3125DGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3125DGVR meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3125DGVR?
All SN74CBTLV3125DGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3125DGVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3125DGVR part is unused and in its original packaging.
Return procedure for SN74CBTLV3125DGVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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