Texas Instruments SN74CBTLV3125PW
- Part No.:
- SN74CBTLV3125PW
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTLV3125PW.pdf
- Description:
- IC BUS SWITCH 1 X 1:1 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:11,725
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Product details
Overview
SN74CBTLV3125PW from Texas Instruments is a low-voltage quadruple FET bus switch with independent 5Ω on-state resistance, rail-to-rail signal switching, and Ioff partial-power-down support. It operates from 2.3V to 3.6V, delivers sub-5ns enable/disable timing, and isolates ports during power-off-used in JTAG/SPI signal routing for enterprise computing and wired networking systems.
For engineers reviewing the SN74CBTLV3125PW datasheet, SN74CBTLV3125PW pinout, SN74CBTLV3125PW application, or SN74CBTLV3125PW equivalent, this page provides verified electrical specs, TSSOP-14 package details, functional mode truth table, isolation behavior under VCC=0, and real-world selection guidance for hot-swap-capable bus switching.
Technical Context
The SN74CBTLV3125PW implements four independent bidirectional analog switches controlled by active-high OE inputs, each forming a low-resistance path between A and B ports when enabled. Its FET-based architecture enables rail-to-rail voltage transfer without level-shifting and supports back-drive protection via Ioff specification.
It features guaranteed 5Ω typical on-resistance at VCC = 2.5V/3.3V with ≤15Ω max across temperature, 0.25ns typical propagation delay, and <5ns enable/disable times. Thermal resistance (RθJA) is 148.9°C/W in its TSSOP-14 package, and it meets JESD 78 Class II latch-up immunity (>100 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 5 Ω typical at VCC = 3.3V, 64mA - ensures minimal voltage drop and signal attenuation in high-speed data paths |
| Supply voltage range | 2.3V to 3.6V - compatible with 2.5V and 3.3V logic domains without external level shifters |
| Ioff current | 10 µA max at VCC = 0V - prevents damaging back-current flow during partial power-down |
| Propagation delay (tpd) | 0.25 ns typical at VCC = 3.3V - preserves signal integrity in >1 Gbps digital interfaces |
| Enable/disable time (ten/tdis) | 2–4.4 ns typical at VCC = 3.3V - enables precise timing control for protocol arbitration and hot-swap sequencing |
| Operating temperature | –40°C to +85°C - validated for industrial-grade embedded and networking equipment |
| ESD rating (HBM) | ±2000 V - meets JEDEC JS-001 for robust handling in automated assembly and field service |
Pinout & Package
TSSOP-14 (PW) package: 5.00 mm × 4.40 mm body, 0.65 mm lead pitch, surface-mount, moisture-sensitive Level-1 (260°C, unlimited reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 2OE, 3OE, 4OE | Active-high enable input | Drives corresponding switch into high-Z state when high; ties to VCC via pullup for power-up safety |
| 1A–4A, 1B–4B | Bidirectional I/O port pair | Passes rail-to-rail signals (0–3.6V) with <5Ω resistance; no directionality or buffering |
| VCC | Power supply | Single 2.3–3.6V supply powers all four switches and control logic; requires local 0.1µF decoupling |
| GND | Ground reference | Common return for all channels and internal circuitry; must be low-inductance connection |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Supports full 0–VCC signal swing on A/B ports without clipping or distortion |
| Ioff partial-power-down protection | Blocks >99.9% of back-current when VCC = 0, enabling safe live insertion in multi-rail systems |
| Low on-resistance (5Ω typ) | Minimizes insertion loss and maintains signal edge rate in high-frequency data buses |
| Independent channel control | Each of four OE pins enables/disables its own A–B path-no shared enable or inter-channel coupling |
| Latch-up immunity >100 mA | Complies with JESD 78 Class II, ensuring reliability in noisy industrial environments |
Applications
| Protocol Isolation | JTAG Debug Routing |
|---|---|
Use Scenario: Isolating SPI flash and RAM interfaces from a host processor during firmware update or diagnostics. IC Role / Device Role / Timing Role: Bidirectional bus switch enabling/disabling signal paths under software control via discrete OE lines. Use Value: Prevents bus contention during concurrent access; eliminates need for sequenced power-up of peripherals. |
Use Scenario: Sharing a single JTAG debug header among multiple SoCs on a server motherboard. IC Role / Device Role / Timing Role: Low-latency, direction-agnostic signal router that passes TCK/TMS/TDI/TDO without buffering or delay skew. Use Value: Enables hot-plug debug access without resetting other subsystems; supports Ioff-powered-off isolation. |
| Hot-Swap Peripheral Enable | GPIO Multiplexing |
Use Scenario: Safely connecting/disconnecting PCIe add-in cards or mezzanine modules while main system remains powered. IC Role / Device Role / Timing Role: Signal gate activated only when module presence and power status are confirmed. Use Value: Eliminates risk of back-driving powered-off logic; avoids ESD-triggered latch-up during insertion. |
Use Scenario: Reassigning MCU GPIO pins between UART, I²C, and general-purpose functions in building automation controllers. IC Role / Device Role / Timing Role: Passive analog switch selecting which peripheral connects to shared pin resources. Use Value: Reduces PCB layer count by avoiding dedicated routing; maintains signal integrity up to 200 MHz. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar FET bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3245PWR | Octal (8-channel), 3-state output architecture with common OE; higher channel count but no per-channel enable | Suitable for wide-bus isolation (e.g., 8-bit parallel interfaces); not ideal for independent per-port control | Choose SN74CBTLV3245PWR when consolidating multiple signals under one enable, not for granular channel gating. |
| TS3A24159RGTR | 2-channel, 0.7Ω ron, 3.6V max, ±25V fault protection; supports higher voltage tolerance and lower resistance | Used where overvoltage resilience or ultra-low loss is critical (e.g., audio line switching); lacks Ioff spec | Choose TS3A24159RGTR for fault-tolerant analog paths; avoid if partial-power-down isolation is required. |
Compared with SN74CBTLV3125PW, SN74CBTLV3245PWR offers higher integration but less flexible control, while TS3A24159RGTR trades Ioff safety for lower ron and voltage margin-neither is pin-compatible, and both require layout revision for substitution.
Availability
SN74CBTLV3125PW is available at Aetrix Electronics and suitable for enterprise computing, wired networking, and building automation requiring stable component supply and long-term industrial lifecycle support.
Supply support for SN74CBTLV3125PW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with focus on reliability, precision, and energy efficiency.
The SN74CBTLV3125PW belongs to TI's CBTLV logic family, engineered for low-voltage, high-speed bus switching in datacenter, telecom, and industrial control systems where signal integrity and power-aware isolation are critical.
FAQ
What is the maximum operating temperature for SN74CBTLV3125PW?
The SN74CBTLV3125PW is rated for operation from –40°C to +85°C ambient temperature. This range applies specifically to the TSSOP-14 (PW) package variant and is validated per JEDEC JESD51 thermal testing standards. Operation beyond 85°C may cause parametric drift or reduced reliability; derating is recommended above 70°C for continuous use.
Does SN74CBTLV3125PW support true bidirectional signal flow?
Yes, SN74CBTLV3125PW supports fully bidirectional analog signal routing between each A and B port pair. There is no internal directionality or buffering-signals pass with rail-to-rail voltage range and symmetric on-resistance (5Ω typical), making it suitable for differential pairs, clock distribution, and data bus isolation without polarity assumptions.
How does the Ioff feature protect SN74CBTLV3125PW during partial power-down?
The Ioff feature in SN74CBTLV3125PW limits off-state current to ≤10 µA when VCC = 0V and any I/O port is biased between 0–3.6V. This prevents damaging back-current from externally powered circuits into the unpowered device, enabling safe hot-swap and live-insertion scenarios without requiring complex power sequencing.
What is the recommended pull-up resistor value for OE pins on SN74CBTLV3125PW?
Texas Instruments recommends tying each OE pin of SN74CBTLV3125PW to VCC via a pullup resistor to ensure high-impedance state at power-up. The minimum value depends on the driver's sink capability; for standard CMOS drivers, 10 kΩ is typical. Values below 1 kΩ increase static current but improve noise immunity; values above 100 kΩ risk floating states in noisy environments.
Can SN74CBTLV3125PW be used with 1.8V logic signals?
Yes, SN74CBTLV3125PW supports 1.8V logic levels on its I/O ports when VCC ≥ 2.3V. Its rail-to-rail switching allows full 0–VCC signal swing, and its control inputs accept VIH = 2.0V min at VCC = 3.6V-compatible with 1.8V-tolerant microcontrollers driving OE through level-shifted or open-drain interfaces.
SN74CBTLV3125PW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Bus Switch
- Circuit:
- 1 x 1:1
- Independent Circuits:
- 4
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
SN74CBTLV3125PW FAQ
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5.How can I obtain technical support or documentation for SN74CBTLV3125PW?
For technical support, including SN74CBTLV3125PW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV3125PW requirements.
6.How does Aetrix verify that SN74CBTLV3125PW is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3125PW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3125PW meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3125PW?
All SN74CBTLV3125PW units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3125PW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3125PW part is unused and in its original packaging.
Return procedure for SN74CBTLV3125PW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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