Texas Instruments SN74CBTLV3384DWR
- Part No.:
- SN74CBTLV3384DWR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
SN74CBTLV3384DWR.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,904
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74CBTLV3384DWR from Texas Instruments is a low-voltage 10-bit FET bus switch in SOIC-24 package, featuring 5-Ω on-state resistance, rail-to-rail switching, and Ioff support for partial-power-down mode. It operates from 2.3 V to 3.6 V and delivers sub-nanosecond propagation delay (0.15 ns typical at 2.5 V), enabling high-speed data routing in memory expansion and processor interconnect applications.
For engineers reviewing the SN74CBTLV3384DWR datasheet, SN74CBTLV3384DWR pinout, SN74CBTLV3384DWR application, or SN74CBTLV3384DWR equivalent, key selection criteria include guaranteed 5-Ω ron across voltage range, dual 5-bit independent enable control, Ioff leakage <10 μA at VCC = 0 V, and SOIC-24 thermal performance (θJA = 46°C/W).
Technical Context
The SN74CBTLV3384DWR implements two independent 5-bit FET-based analog switches with separate OE inputs, allowing flexible configuration as either two 5-bit or one 10-bit switch. Its CMOS-compatible control logic supports VIH/VIL thresholds scaled to VCC (e.g., VIH = 2.0 V min at VCC = 3.6 V), ensuring robust noise margin in mixed-voltage systems.
Rail-to-rail signal handling enables full-swing data transfer between A and B ports without level translation, while the Ioff feature actively blocks back-current flow when VCC = 0 V-critical for hot-swap and power-gating architectures. Latch-up immunity exceeds 250 mA per JESD 17, and ESD protection meets 2000-V HBM and 200-V MM standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.3 V to 3.6 V - Enables operation in 2.5 V and 3.3 V logic domains without external level shifters. |
| ron (Typical) | 5 Ω - Ensures minimal voltage drop and signal distortion during high-speed data pass-through. |
| tpd (Typical) | 0.15 ns - Supports >5 GHz effective switching bandwidth for DDR memory and parallel bus applications. |
| Ioff (Max) | 10 μA at VCC = 0 V - Prevents damaging backflow current during partial power-down, protecting upstream drivers. |
| Switch Isolation | Cio(OFF) = 10 pF - Limits capacitive coupling between ports in high-impedance state, reducing crosstalk. |
| ESD Rating | 2000-V HBM - Provides robust handling during board assembly and field service without additional protection circuitry. |
| θJA | 46°C/W (SOIC-DW) - Allows sustained 128 mA channel current under standard PCB layout conditions. |
Pinout & Package
SN74CBTLV3384DWR uses a 24-pin SOIC (DW) package with 1.27 mm pitch, 7.5 mm × 15.4 mm body, and 46°C/W thermal resistance. Pin 1 is located at top-left corner with index marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE | Enable input for first 5-bit switch | Active-low control: drives A1–A5 ↔ B1–B5 path when low; high-impedance when high. |
| 1A1–1A5 | Input/output port A (first 5-bit group) | Bidirectional data terminals with rail-to-rail voltage handling (−0.5 V to 4.6 V). |
| 1B1–1B5 | Input/output port B (first 5-bit group) | Electrically identical to 1A pins; connected to 1A pins only when 1OE = low. |
| GND | Ground reference | Common return for all internal FET sources and bias circuitry; must be low-impedance. |
| VCC | Supply voltage | Power rail for internal level-shifting and output buffers; decoupling capacitor required near pin. |
| 2A1–2A5 | Input/output port A (second 5-bit group) | Independent 5-bit channel, controlled by 2OE; electrically isolated from first group when disabled. |
| 2B1–2B5 | Input/output port B (second 5-bit group) | Matches 1B functionality; no internal connection to 1B pins. |
| 2OE | Enable input for second 5-bit switch | Independent control allows asymmetric bus partitioning (e.g., 5-bit + 10-bit hybrid configurations). |
Key Features
| Feature | Design Value |
|---|---|
| Low on-state resistance | 5 Ω typical ensures <50 mV drop at 10 mA, preserving signal integrity in 3.3 V LVCMOS interfaces. |
| Rail-to-rail switching | Supports −0.5 V to 4.6 V I/O voltage range, enabling direct connection to legacy 5 V-tolerant peripherals without clamping diodes. |
| Ioff partial-power-down | Blocks back-current flow when VCC = 0 V, allowing safe insertion/removal in live backplanes and modular systems. |
| Dual independent enables | 1OE and 2OE allow granular power management-e.g., disable one 5-bit segment while keeping the other active for debug access. |
| Latch-up immunity | Exceeds 250 mA per JESD 17, eliminating need for external current-limiting resistors in high-noise industrial environments. |
Applications
| Memory Expansion Interface | Processor Local Bus Multiplexing |
|---|---|
Use Scenario: Adding external SRAM or Flash to microcontroller with limited address/data pins. IC Role / Device Role / Timing Role: Bidirectional 10-bit data path switch that routes shared address/data bus between MCU and memory devices. Use Value: Eliminates need for discrete transceivers; 5-Ω ron preserves setup/hold timing margins at 100 MHz bus speeds. | Use Scenario: Sharing a 10-bit peripheral bus among multiple ASICs in an embedded controller subsystem. IC Role / Device Role / Timing Role: High-speed analog bus gate isolating competing masters during arbitration cycles. Use Value: Sub-ns tpd prevents bus contention-induced glitches; Ioff prevents power-domain leakage during idle periods. |
| Hot-Swappable Module Interconnect | Legacy Peripheral Voltage Translation |
Use Scenario: Backplane interface where daughter cards are inserted/removed while system remains powered. IC Role / Device Role / Timing Role: Isolation barrier between mainboard and module, activated only during valid link negotiation. Use Value: Ioff blocks backfeed from powered modules into unpowered slots, meeting IEC 61000-4-2 surge immunity requirements. | Use Scenario: Connecting 2.5 V FPGA I/O to 3.3 V legacy peripherals (e.g., UART, SPI EEPROM). IC Role / Device Role / Timing Role: Passive voltage-agnostic bus switch enabling bidirectional data flow without direction control signals. Use Value: Rail-to-rail operation avoids logic-level ambiguity; 10 pF Cio(OFF) limits capacitive loading on 3.3 V side during FPGA reset sequences. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384DWR | Higher VCC max (5.5 V), higher ron (7 Ω typ), no Ioff support. | Requires external power sequencing for hot-swap; unsuitable for partial-power-down systems. | Choose when interfacing with 5 V logic and Ioff is not required. |
| SN74LVC1G3157DCKR | Single-channel SPDT, 3.3 V only, ron = 10 Ω, smaller SC70-6 package. | Not scalable to 10-bit width; requires 10x units for equivalent function, increasing board area and routing complexity. | Choose only for ultra-low-density point-to-point switching where space is critical and channel count is ≤2. |
Compared with SN74CBTLV3384DWR, SN74CBT3384DWR trades Ioff and low ron for wider voltage range, while SN74LVC1G3157DCKR sacrifices integration density and performance for footprint reduction-neither offers pin-compatible replacement or identical functional scope.
Availability
SN74CBTLV3384DWR is available at Aetrix Electronics and suitable for memory expansion, processor bus multiplexing, hot-swappable module interconnect, and legacy peripheral voltage translation requiring stable component supply and long-term industrial availability.
Supply support for SN74CBTLV3384DWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal technologies, with over 90 years of innovation in industrial, automotive, and communications markets.
The SN74CBTLV3384DWR belongs to TI's CBTLV (low-voltage BiCMOS transistor logic) bus switch family, designed specifically for high-speed, low-distortion data routing in space-constrained, power-sensitive embedded systems.
FAQ
What is the maximum continuous current rating for each channel of the SN74CBTLV3384DWR?
The SN74CBTLV3384DWR supports a continuous channel current of 128 mA per switch path, verified under recommended operating conditions (VCC = 2.3 V to 3.6 V). This rating assumes proper PCB thermal design with adequate copper pour and is specified in the absolute maximum ratings table of the official datasheet SCDS059G. Exceeding this current may degrade ron stability or trigger thermal shutdown in sustained operation.
Does the SN74CBTLV3384DWR require external pull-up resistors on its OE pins?
Yes, to ensure high-impedance state during power-up or power-down, OE pins of the SN74CBTLV3384DWR must be tied to VCC through a pull-up resistor. The minimum value depends on the current-sinking capability of the driving source, as stated in the device's functional description. TI recommends verifying driver strength against the 10 μA Ioff specification to avoid unintended switch activation during brown-out conditions.
Can the SN74CBTLV3384DWR operate with 2.5 V and 3.3 V supplies simultaneously on different ports?
No-the SN74CBTLV3384DWR has a single VCC pin powering all internal circuitry, so both A and B ports share the same supply domain. However, its rail-to-rail I/O structure (−0.5 V to 4.6 V) allows it to pass signals between 2.5 V and 3.3 V logic families without level translation, provided VCC is set to the higher voltage (e.g., 3.3 V) and all signals remain within absolute maximum ratings.
How does the Ioff feature of the SN74CBTLV3384DWR protect downstream circuitry?
The Ioff feature of the SN74CBTLV3384DWR limits leakage current to ≤10 μA when VCC = 0 V and any I/O pin is biased between 0 V and 3.6 V. This prevents damaging reverse current flow from powered buses into unpowered sections of a system-critical in modular designs where one board may be hot-plugged while others remain active. The protection is inherent to the FET architecture and requires no external components.
Is the SN74CBTLV3384DWR RoHS compliant and lead-free?
Yes, the SN74CBTLV3384DWR is RoHS compliant and features NiPdAu (NIPDAU) lead finish, as confirmed in TI's Package Option Addendum. It meets JEDEC Level-1 reflow profile (260°C peak, unlimited floor life) and is rated for industrial temperature range (−40°C to 85°C). Full compliance documentation-including material declarations and test reports-is available via TI's Quality & Environmental page using the orderable part number SN74CBTLV3384DWR.
SN74CBTLV3384DWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 24-SOIC (0.295", 7.50mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SOIC
SN74CBTLV3384DWR FAQ
1.How can I place an order for SN74CBTLV3384DWR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBTLV3384DWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBTLV3384DWR reliable?
The price and inventory of SN74CBTLV3384DWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTLV3384DWR is usually 5 days.
3.What payment methods are accepted for SN74CBTLV3384DWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74CBTLV3384DWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74CBTLV3384DWR?
SN74CBTLV3384DWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74CBTLV3384DWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74CBTLV3384DWR?
For technical support, including SN74CBTLV3384DWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV3384DWR requirements.
6.How does Aetrix verify that SN74CBTLV3384DWR is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3384DWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3384DWR meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3384DWR?
All SN74CBTLV3384DWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3384DWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3384DWR part is unused and in its original packaging.
Return procedure for SN74CBTLV3384DWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74CBTLV3384DWR Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
