Texas Instruments SN74CBTLV3861DBQR
- Part No.:
- SN74CBTLV3861DBQR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-SSOP (0.154", 3.90mm Width)
- Datasheet:
-
SN74CBTLV3861DBQR.pdf
- Description:
- IC BUS SW 10 X 1:1 24SSOP/QSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,412
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74CBTLV3861DBQR from Texas Instruments is a 10-bit high-speed bus switch IC with 5-Ω on-state resistance, rail-to-rail signal switching, and Ioff partial-power-down support. It operates from 2.3 V to 3.6 V and delivers sub-nanosecond propagation delay (0.15 ns typ at 2.5 V), enabling low-latency interconnect in memory expansion, FPGA I/O bridging, and hot-swap data path isolation.
For engineers reviewing the SN74CBTLV3861DBQR datasheet, SN74CBTLV3861DBQR pinout, SN74CBTLV3861DBQR application, or SN74CBTLV3861DBQR equivalent, key selection criteria include guaranteed 5 Ω ron at 2.5 V/3.3 V, 10 µA Ioff leakage at VCC = 0 V, flow-through pinout for PCB layout optimization, and JESD78 Class II latch-up immunity.
Technical Context
This device implements a 10-bit bidirectional analog switch architecture with independent A/B port connectivity controlled by a single active-low OE input. Its CMOS transmission-gate design enables rail-to-rail voltage transfer without level shifting, supporting both digital and analog signal pass-through up to 3.6 V.
The Ioff feature actively blocks current backflow when VCC = 0 V, ensuring system-level isolation during partial power-down sequences. Latch-up immunity exceeds 100 mA per JESD 78 Class II, and the flow-through package layout minimizes trace crosstalk and stub length in high-speed routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 5 Ω typical at VCC = 2.5 V, 0 V input - ensures minimal voltage drop and signal distortion in high-current data paths |
| Propagation delay (tpd) | 0.15 ns typical at VCC = 2.5 V - enables sub-ns timing closure in DDR memory buffers and FPGA interconnects |
| Ioff leakage | 10 µA max at VCC = 0 V, VI/O = 0–3.6 V - guarantees safe isolation during power sequencing and hot-plug events |
| Supply voltage range | 2.3 V to 3.6 V - compatible with 2.5 V and 3.3 V logic domains without external level shifters |
| Operating temperature | −40°C to +85°C - qualified for industrial-grade embedded systems and communications infrastructure |
| Input capacitance (Ci) | 3 pF - reduces loading on driving sources and preserves signal integrity in high-frequency buses |
| Channel current rating | 128 mA continuous - supports robust drive capability for multi-load fanout applications |
Pinout & Package
SN74CBTLV3861DBQR is housed in a 24-pin SSOP (DBQ) package with 0.65 mm pitch, 7.9 mm × 6.2 mm body size, and 1.2 mm maximum height. The flow-through pin arrangement places A1–A10 on pins 2–11, B1–B10 on pins 14–23, OE on pin 13, VCC on pin 12, and GND on pin 11 - minimizing PCB trace length and skew between corresponding A/B pairs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | No internal connection (NC) | Unused pad; must remain unconnected to avoid parasitic coupling or mechanical stress |
| 2–11 | A1–A10 inputs/outputs | Port A side of 10-bit bidirectional switch; electrically identical to B-side for analog/digital signal pass-through |
| 12 | VCC | Positive supply input; decoupling capacitor required within 10 mm for stable high-speed operation |
| 13 | OE (active-low) | Output enable control; tie to VCC via pullup resistor during power-up to ensure high-impedance default state |
| 14–23 | B1–B10 inputs/outputs | Port B side of 10-bit bidirectional switch; matched ron and timing to A-side for symmetrical performance |
| 24 | GND | Ground reference; connect directly to solid ground plane beneath package for EMI and noise suppression |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Supports full 0 V to VCC signal swing without clipping - essential for mixed-signal I/O buffering and ADC/DAC interface isolation |
| Flow-through pinout | Linear A1–A10 → B1–B10 layout eliminates crossing traces and reduces differential pair skew in parallel bus routing |
| Ioff partial-power-down protection | Prevents backdrive current into powered-down subsystems - critical for modular hot-swap architectures and power-gated SoC domains |
| JESD 78 Class II latch-up immunity | Withstands >100 mA fault current without destructive latch-up - ensures reliability in noisy industrial environments |
| Low 3 pF input capacitance | Minimizes capacitive loading on upstream drivers, preserving rise/fall times in >100 MHz data buses |
Applications
| Memory Expansion Interface | FPGA I/O Bridging |
|---|---|
|
Use Scenario: Isolating DDR2/DDR3 address/control lines between CPU and memory modules during dynamic reconfiguration. IC Role / Device Role / Timing Role: Bidirectional bus switch enabling on-demand connection/disconnection of memory banks without signal degradation. Use Value: 5 Ω ron and 0.15 ns tpd maintain timing margins across 400+ MHz memory clocks while Ioff prevents power domain conflict during bank disable. |
Use Scenario: Routing configurable I/O signals between FPGA banks operating at different voltage levels (2.5 V/3.3 V). IC Role / Device Role / Timing Role: Voltage-transparent signal pass-through switch that preserves logic thresholds and edge rates without level translation. Use Value: Rail-to-rail operation and 3 pF Ci allow direct connection to FPGA I/O cells, eliminating need for discrete level shifters and reducing BOM count. |
| Hot-Swap Backplane Interconnect | PCI Express Lane Multiplexing |
|
Use Scenario: Enabling safe insertion/removal of line cards in telecom chassis while main backplane remains powered. IC Role / Device Role / Timing Role: Signal isolation gate activated only after power stabilization and firmware handshake completes. Use Value: Ioff < 10 µA at VCC = 0 V blocks backfeed from live backplane into unpowered card, satisfying IEC 61000-4-2 ESD and hot-swap safety requirements. |
Use Scenario: Dynamically assigning PCIe Gen2 lanes between GPU, NVMe, and network controllers in server motherboards. IC Role / Device Role / Timing Role: Low-latency, low-distortion analog switch enabling lane reallocation without PCIe link reset. Use Value: Sub-ns tpd and matched ron across all 10 bits preserve PCIe eye diagram integrity, supporting 5 GT/s signaling without equalization penalty. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3245DBQR | 8-bit configuration, identical ron (5 Ω), same DBQ package and Ioff spec | Limited to 8-bit buses; insufficient for 10-bit memory or control interfaces requiring full width | Select when system bus width is ≤8 bits and footprint compatibility with SN74CBTLV3861DBQR is required |
| SN74CBT3245DBQR | Non-LV version: higher ICC (100 µA vs. 10 µA), wider VCC range (4.5–5.5 V), no Ioff support | Not suitable for partial-power-down systems; incompatible with 2.5 V/3.3 V-only designs | Choose only for legacy 5 V logic systems where Ioff and low-voltage operation are not required |
Compared with SN74CBTLV3245DBQR and SN74CBT3245DBQR, SN74CBTLV3861DBQR uniquely delivers 10-bit width with Ioff-enabled partial-power-down safety and 2.3–3.6 V operation - making it the sole option for modern low-voltage, high-density bus isolation where bit count and power sequencing integrity are jointly critical.
Availability
SN74CBTLV3861DBQR is available at Aetrix Electronics and suitable for memory expansion interfaces, FPGA I/O bridging, hot-swap backplane interconnects, and PCIe lane multiplexing requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant packaging.
Supply support for SN74CBTLV3861DBQR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in high-speed interface ICs and industrial-grade reliability.
The SN74CBTLV3861DBQR belongs to TI's CBTLV (ColdBond™ Low-Voltage) logic family, engineered specifically for low-voltage, high-bandwidth bus switching in space-constrained, thermally demanding applications such as networking equipment and programmable logic systems.
FAQ
What is the maximum continuous current rating per channel for SN74CBTLV3861DBQR?
The SN74CBTLV3861DBQR supports a continuous channel current of 128 mA per switch path. This rating is validated under thermal conditions defined in the absolute maximum ratings table and ensures reliable operation without derating when used within the recommended 2.3 V–3.6 V supply range and −40°C to +85°C ambient temperature. Exceeding this current may cause thermal runaway or permanent damage to the SN74CBTLV3861DBQR.
Does SN74CBTLV3861DBQR support true bidirectional signal flow without direction control pins?
Yes, SN74CBTLV3861DBQR provides fully bidirectional analog switching between A and B ports with no direction pin required. Its transmission-gate architecture allows signals to pass equally well from A to B or B to A when OE is low. This eliminates timing-critical direction control logic and simplifies PCB routing - a core design advantage confirmed in the functional table and logic diagram of the SN74CBTLV3861DBQR datasheet.
How should the OE pin be handled during power-up to prevent undefined states on SN74CBTLV3861DBQR?
To ensure high-impedance state at power-up, OE on SN74CBTLV3861DBQR must be tied to VCC through an external pullup resistor. TI specifies the minimum resistor value based on the current-sinking capability of the driving source - typically 10 kΩ suffices for most microcontroller GPIOs. Leaving OE floating or uncontrolled risks unintended conduction and potential bus contention, which is explicitly warned against in the SN74CBTLV3861DBQR datasheet.
Is SN74CBTLV3861DBQR compatible with 1.8 V logic systems?
No, SN74CBTLV3861DBQR is not rated for 1.8 V operation. Its recommended supply range is strictly 2.3 V to 3.6 V, and its input thresholds (VIH = 1.7 V min at VCC = 2.3 V) do not guarantee reliable recognition of 1.8 V logic highs. Attempting to operate SN74CBTLV3861DBQR below 2.3 V may result in increased ron, timing violations, or functional failure. For 1.8 V systems, consider TI's SN74AVC series instead.
What is the thermal resistance (θJA) of the SN74CBTLV3861DBQR in its DBQ package?
The junction-to-ambient thermal resistance (θJA) for SN74CBTLV3861DBQR in the DBQ package is 61°C/W, as specified in the absolute maximum ratings table. This value assumes standard JEDEC test board conditions (2-layer board, 1-in² copper). Actual thermal performance depends on PCB layout - adding thermal vias under the exposed pad (if present) and increasing copper area can reduce effective θJA by up to 20°C/W in optimized designs.
SN74CBTLV3861DBQR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 24-SSOP (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 10 x 1:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-SSOP
SN74CBTLV3861DBQR FAQ
1.How can I place an order for SN74CBTLV3861DBQR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBTLV3861DBQR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBTLV3861DBQR reliable?
The price and inventory of SN74CBTLV3861DBQR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTLV3861DBQR is usually 5 days.
3.What payment methods are accepted for SN74CBTLV3861DBQR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74CBTLV3861DBQR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74CBTLV3861DBQR?
SN74CBTLV3861DBQR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74CBTLV3861DBQR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74CBTLV3861DBQR?
For technical support, including SN74CBTLV3861DBQR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV3861DBQR requirements.
6.How does Aetrix verify that SN74CBTLV3861DBQR is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3861DBQR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3861DBQR meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3861DBQR?
All SN74CBTLV3861DBQR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3861DBQR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3861DBQR part is unused and in its original packaging.
Return procedure for SN74CBTLV3861DBQR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74CBTLV3861DBQR Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

