Texas Instruments SN74CBTLV3861PWE4
- Part No.:
- SN74CBTLV3861PWE4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTLV3861PWE4.pdf
- Description:
- IC SWITCH BUS FET 10BIT 24-TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,040
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74CBTLV3861PWE4 from Texas Instruments is a 10-bit high-speed bus switch IC with 5-Ω on-state resistance, rail-to-rail signal switching, and Ioff partial-power-down support. It operates from 2.3 V to 3.6 V and delivers sub-nanosecond propagation delay (0.15 ns typ at 2.5 V), enabling low-latency data path isolation in memory expansion and FPGA I/O buffering applications.
For engineers reviewing the SN74CBTLV3861PWE4 datasheet, SN74CBTLV3861PWE4 pinout, SN74CBTLV3861PWE4 application, or SN74CBTLV3861PWE4 equivalent, key selection criteria include guaranteed 5 Ω ron across voltage range, flow-through pinout for PCB layout optimization, Ioff leakage <10 µA during power-down, and TSSOP-24 package compatibility with high-density routing.
Technical Context
This device implements a passive FET-based bus switch architecture-no internal logic or level translation-enabling bidirectional, voltage-transparent signal routing between A and B ports. Its OE-controlled enable/disable behavior provides deterministic high-impedance isolation without latch-up risk (exceeds 100 mA per JESD 78 Class II).
The flow-through pinout (A1–A10 left side, B1–B10 right side, OE/VCC/GND centrally located) minimizes trace skew and crosstalk in parallel bus implementations. Ioff protection ensures no backflow current when VCC = 0 V and port voltages range from 0 to 3.6 V, supporting hot-swap and partial-power-down system architectures.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 5 Ω typical at VCC = 2.5 V, VI = 0 V, II = 24 mA - enables minimal voltage drop and signal integrity in 3.3 V/2.5 V bus interfaces |
| Propagation delay (tpd) | 0.15 ns typical at VCC = 2.5 V - supports >5 GHz effective switching bandwidth for high-speed data paths |
| Ioff leakage current | 10 µA max at VCC = 0 V, VI/VO = 0–3.6 V - prevents damaging back-current during partial power-down sequences |
| Supply voltage range | 2.3 V to 3.6 V - compatible with 2.5 V and 3.3 V logic families without level shifters |
| Input capacitance (Ci) | 3 pF typical - reduces loading on driving sources and preserves edge rate in multi-drop buses |
| Off-state capacitance (Cio) | 5 pF typical at OE = VCC - maintains low crosstalk and signal coupling between isolated ports |
| Operating temperature | −40°C to +85°C - qualified for industrial-grade embedded systems and communications equipment |
Pinout & Package
TSSOP-24 (PW) package: 7.8 mm × 4.4 mm, 1.2 mm max height, 0.65 mm pitch, lead-free NiPdAu finish, MSL Level-1 (260°C, unlimited reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 24 | No internal connection (NC) | Unused pins; must be left floating or grounded per layout best practice - no electrical function |
| 2–11 (A1–A10) | Port A input/output terminal | Bidirectional data path terminal; connects directly to source-side bus (e.g., processor or FPGA output) |
| 13–22 (B1–B10) | Port B input/output terminal | Bidirectional data path terminal; connects directly to sink-side bus (e.g., memory or peripheral interface) |
| 12 | GND | Power return reference for all switching FETs and control circuitry - requires low-inductance grounding |
| 23 | VCC | Positive supply for internal bias and OE logic - must be decoupled locally with 0.1 µF ceramic capacitor |
| 13 | OE | Active-low output enable - drives switch ON (A↔B connected) when low; high-impedance isolation when high |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Supports full 0 V to VCC signal swing without distortion - preserves logic high/low margins in mixed-voltage systems |
| Flow-through pinout architecture | Minimizes PCB trace length and layer transitions - reduces skew, EMI, and routing congestion in 10-bit parallel buses |
| Ioff partial-power-down protection | Blocks reverse current flow when VCC = 0 V - eliminates need for external isolation diodes in modular power domains |
| Latch-up immunity | Exceeds 100 mA per JESD 78 Class II - ensures robust operation under transient overvoltage or ground bounce conditions |
| Low dynamic power consumption | ICC = 10 µA max at VCC = 3.6 V - reduces quiescent load on power rails in always-on subsystems |
Applications
| Memory Expansion Interface | FPGA I/O Buffering |
|---|---|
|
Use Scenario: Isolating address/data lines between microcontroller and external SRAM/Flash during power sequencing. IC Role / Device Role / Timing Role: Bidirectional bus switch enabling dynamic connection/disconnection of memory bus segments. Use Value: Prevents back-driving during MCU reset or sleep modes via Ioff, eliminating data corruption and supply contention. |
Use Scenario: Routing configurable I/O signals from FPGA banks to multiple peripheral modules with shared bus topology. IC Role / Device Role / Timing Role: Low-latency, voltage-transparent signal gate controlling physical layer connectivity. Use Value: Enables sub-ns timing margin preservation and eliminates level-shifter complexity in 2.5 V/3.3 V mixed-FPGA designs. |
| Hot-Swappable Module Interconnect | Test Access Port Multiplexing |
|
Use Scenario: Enabling safe insertion/removal of PCIe or USB add-in cards while main system remains powered. IC Role / Device Role / Timing Role: Signal isolation barrier activated only during module presence detection and power ramp-up. Use Value: Guarantees zero back-current injection into live backplane traces using Ioff specification, meeting hot-swap safety requirements. |
Use Scenario: Sharing JTAG or SWD debug interface among multiple SoCs on a single test fixture board. IC Role / Device Role / Timing Role: Manual or firmware-controlled multiplexer selecting active debug target without signal contention. Use Value: Maintains clean TCK/TMS waveform integrity (<0.25 ns tpd) and eliminates cross-talk-induced false clocking during probe switching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3244DBR | 8-bit configuration, higher ron (7 Ω typ), same TSSOP-20 package | Lower channel count; suitable for narrower data paths where space constraints favor smaller footprint | Select when 8-bit width suffices and board area is critical - not pin-compatible with SN74CBTLV3861PWE4 |
| SN74LVC1G3157DCKR | Single-pole double-throw (SPDT) switch, 6 Ω ron, SC70-6 package | Discrete channel switching instead of parallel bus; optimized for signal routing rather than data bus isolation | Choose for point-to-point analog/digital signal selection - requires 10x devices to match 10-bit functionality |
Compared with SN74CBTLV3861PWE4, SN74CBT3244DBR offers reduced pin count and area but lacks 10-bit width and sub-0.2 ns tpd; SN74LVC1G3157DCKR provides superior flexibility per channel yet incurs significant layout overhead and timing skew in parallel configurations.
Availability
SN74CBTLV3861PWE4 is available at Aetrix Electronics and suitable for memory expansion interfaces, FPGA I/O buffering, hot-swappable module interconnects, and test access port multiplexing requiring stable component supply, industrial temperature operation, and long-term lifecycle continuity.
Supply support for SN74CBTLV3861PWE4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and digital signal technologies, with decades of expertise in high-reliability logic and interface solutions.
The SN74CBTLV3861PWE4 belongs to TI's CBTLV (CrossBar TTL) bus switch family, engineered for ultra-low on-resistance and nanosecond-speed signal routing in high-density digital systems.
FAQ
What is the maximum operating frequency supported by the SN74CBTLV3861PWE4?
The SN74CBTLV3861PWE4 does not specify a maximum clock frequency because it is an analog bus switch-not a clocked logic device. Its 0.15 ns typical propagation delay (tpd) enables reliable operation with data edges faster than 5 GHz, making it suitable for DDR2/DDR3 address/control buses and high-speed FPGA interconnects where signal integrity depends on minimal ron and Cio.
Can the SN74CBTLV3861PWE4 be used with 1.8 V logic signals?
No-the SN74CBTLV3861PWE4 requires VCC between 2.3 V and 3.6 V and is not rated for 1.8 V operation. Applying 1.8 V signals while VCC ≥ 2.3 V is acceptable for rail-to-rail switching, but the device itself cannot be powered from 1.8 V. For 1.8 V systems, consider TI's SN74AVC series or dedicated level translators instead of the SN74CBTLV3861PWE4.
How should OE be handled during power-up to ensure defined state?
To guarantee high-impedance state at power-up, OE must be held high until VCC stabilizes. TI recommends tying OE to VCC through a pull-up resistor; minimum value is determined by the driver's current-sinking capability. For robustness, use a 10 kΩ resistor and avoid leaving OE floating-undefined OE state may cause momentary bus contention before power stabilization in the SN74CBTLV3861PWE4.
Does the SN74CBTLV3861PWE4 support hot-swap applications?
Yes-the SN74CBTLV3861PWE4 is explicitly designed for hot-swap use via its Ioff feature: when VCC = 0 V, leakage remains ≤10 µA even with port voltages up to 3.6 V. This prevents back-current flow into unpowered sections, satisfying key safety requirements for modular backplane and pluggable card architectures using the SN74CBTLV3861PWE4.
Is there an automotive-qualified version of the SN74CBTLV3861PWE4?
Yes-the SN74CBTLV3861-Q1 is the AEC-Q100 qualified automotive variant of this device, rated for −40°C to +125°C operation and manufactured under TS 16949 processes. It shares identical electrical specifications and pinout with the SN74CBTLV3861PWE4 but adds extended reliability testing, enhanced traceability, and automotive-specific qualification documentation.
SN74CBTLV3861PWE4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 10 x 1:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
SN74CBTLV3861PWE4 FAQ
1.How can I place an order for SN74CBTLV3861PWE4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBTLV3861PWE4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBTLV3861PWE4 reliable?
The price and inventory of SN74CBTLV3861PWE4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTLV3861PWE4 is usually 5 days.
3.What payment methods are accepted for SN74CBTLV3861PWE4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74CBTLV3861PWE4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74CBTLV3861PWE4?
SN74CBTLV3861PWE4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74CBTLV3861PWE4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74CBTLV3861PWE4?
For technical support, including SN74CBTLV3861PWE4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV3861PWE4 requirements.
6.How does Aetrix verify that SN74CBTLV3861PWE4 is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3861PWE4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3861PWE4 meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3861PWE4?
All SN74CBTLV3861PWE4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3861PWE4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3861PWE4 part is unused and in its original packaging.
Return procedure for SN74CBTLV3861PWE4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74CBTLV3861PWE4 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

