Texas Instruments SN74CBTLV3861PWR
- Part No.:
- SN74CBTLV3861PWR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTLV3861PWR.pdf
- Description:
- IC BUS SWITCH 10 X 1:1 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,738
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74CBTLV3861PWR from Texas Instruments is a 10-bit high-speed bus switch IC with 5-Ω on-state resistance, rail-to-rail switching capability, and Ioff support for partial-power-down mode. It operates from 2.3 V to 3.6 V and delivers sub-nanosecond propagation delay (0.15 ns typical at 2.5 V), enabling low-latency data routing in memory expansion and FPGA I/O bridging applications.
For engineers reviewing the SN74CBTLV3861PWR datasheet, SN74CBTLV3861PWR pinout, SN74CBTLV3861PWR application, or SN74CBTLV3861PWR equivalent, key selection criteria include verified 10-bit flow-through architecture, guaranteed 10 µA Ioff at VCC = 0 V, TSSOP-24 package compatibility, and latch-up immunity exceeding 100 mA per JESD 78 Class II.
Technical Context
This device implements a passive FET-based 10-bit bidirectional bus switch with no internal logic or level-shifting circuitry. Its OE-controlled switching uses complementary MOSFET pairs per channel to achieve symmetric on-resistance and rail-to-rail signal pass-through without voltage translation.
The Ioff feature actively blocks current backflow when VCC = 0 V, ensuring isolation between A and B ports during system power sequencing. The flow-through pinout (A1–A10, B1–B10, OE, VCC, GND) minimizes PCB trace skew and eliminates layer transitions in high-speed routing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 5 Ω typical at VCC = 2.5 V - enables minimal voltage drop and signal integrity for 24 mA drive currents |
| Propagation delay (tpd) | 0.15 ns typical at VCC = 2.5 V - supports >5 GHz effective data rates in point-to-point links |
| Ioff current | 10 µA maximum at VCC = 0 V - guarantees safe hot-swap and partial-power-down operation |
| Supply voltage range | 2.3 V to 3.6 V - compatible with 2.5 V and 3.3 V logic domains without level shifters |
| Channel count | 10-bit unidirectional/bidirectional - provides full byte-wide bus isolation or routing |
| Latch-up immunity | >100 mA per JESD 78 Class II - ensures robustness against transient overcurrent events |
| Input capacitance (Ci) | 3 pF - reduces loading on driving sources and preserves edge rate |
Pinout & Package
TSSOP-24 package (PW), 7.9 mm × 4.5 mm × 1.2 mm max height, lead pitch 0.65 mm, RoHS-compliant NIPDAU finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 (A1–A10) | Port A input/output | Bidirectional data terminal connected directly to one side of internal FET switch |
| 13, 14, 15, 16, 17, 18, 19, 20, 21, 22 (B1–B10) | Port B input/output | Bidirectional data terminal connected directly to opposite side of internal FET switch |
| 12 | VCC | Positive supply for switch control logic and FET bias - must be stable before OE assertion |
| 11 | GND | Reference ground for all I/O and control signals - requires low-impedance connection |
| 23 | OE | Active-low output enable - drives switch ON (A↔B connected) when low, high-impedance when high |
| 24, 2 | NC | No internal connection - must remain unconnected per datasheet |
Key Features
| Feature | Design Value |
|---|---|
| Rail-to-rail analog switching | Supports full VCC to GND signal swing without clipping or distortion - essential for mixed-voltage bus interfacing |
| Flow-through pinout architecture | Minimizes PCB trace length asymmetry and crosstalk - simplifies layout for 10-bit parallel interfaces |
| Ioff partial-power-down protection | Prevents damaging back-current flow when VCC is off - enables safe insertion/removal in live backplanes |
| Low on-state resistance (5 Ω) | Reduces insertion loss and timing skew across all 10 channels - maintains signal fidelity at high frequencies |
| Latch-up immunity >100 mA | Ensures operational reliability under ESD or surge events - meets industrial-grade robustness requirements |
Applications
| Memory Expansion Interface | FPGA I/O Bridging |
|---|---|
Use Scenario: Expanding DRAM address/data bus between controller and additional memory modules in embedded systems. IC Role / Device Role / Timing Role: Bidirectional 10-bit bus switch isolating secondary memory banks during access arbitration. Use Value: Enables zero-latency, rail-to-rail signal pass-through with <0.25 ns propagation delay - preserves setup/hold timing margins. | Use Scenario: Interfacing heterogeneous I/O standards (e.g., 2.5 V ASIC to 3.3 V peripheral) on FPGA carrier boards. IC Role / Device Role / Timing Role: Voltage-domain agnostic signal routing switch controlled by FPGA GPIO. Use Value: Eliminates need for discrete level shifters while maintaining sub-nanosecond timing alignment across all 10 lines. |
| Hot-Swappable Module Backplane | Test Access Port Multiplexing |
Use Scenario: Enabling safe insertion/removal of daughter cards in telecom line cards powered via shared backplane. IC Role / Device Role / Timing Role: Isolation switch placed between backplane bus and module-local bus, controlled by supervisor MCU. Use Value: Ioff limits leakage to ≤10 µA when module is unpowered - prevents corruption of active backplane signals. | Use Scenario: Sharing JTAG or SWD debug interface among multiple SoCs on a multi-core test board. IC Role / Device Role / Timing Role: 10-bit multiplexer selecting between up to four device TDI/TDO/TMS/TCK paths. Use Value: 5 Ω ron ensures minimal signal degradation and jitter accumulation across daisy-chained debug chains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switch applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBTLV3245PWR | 8-bit configuration, identical ron (5 Ω), same TSSOP-24 package and Ioff spec | Suitable only where 8-bit width suffices; lacks two channels for full byte+parity or dual-nibble routing | Select when system bus width is strictly 8 bits and footprint reuse is required |
| SN74CBT3245DBQR | 8-bit, higher ron (7 Ω typ), SSOP-24 package, no Ioff support | Not suitable for partial-power-down systems; requires external power sequencing controls | Choose only for cost-sensitive 8-bit legacy designs where power sequencing is fully managed externally |
Compared with SN74CBTLV3245PWR and SN74CBT3245DBQR, the SN74CBTLV3861PWR uniquely delivers 10-bit width with guaranteed Ioff and 5 Ω ron in TSSOP-24 - making it the sole option for new 10-bit hot-plug or low-skew memory expansion designs.
Availability
SN74CBTLV3861PWR is available at Aetrix Electronics and suitable for memory expansion interfaces, FPGA I/O bridging, hot-swappable module backplanes, and test access port multiplexing requiring stable component supply and long-term industrial availability.
Supply support for SN74CBTLV3861PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 50 years of innovation in high-reliability interface and signal-path components.
The SN74CBTLV3861PWR belongs to TI's CBTLV (ColdBond™ Low-Voltage) logic family, engineered specifically for ultra-low on-resistance, high-speed bus switching in space-constrained, power-aware digital systems.
FAQ
What is the maximum operating frequency supported by SN74CBTLV3861PWR?
The SN74CBTLV3861PWR does not specify a clock frequency but supports signal edges with sub-nanosecond propagation delay (0.15 ns typical). Its 5 Ω ron and 3 pF input capacitance enable clean transmission of signals with rise times down to ~100 ps, making it suitable for data rates exceeding 5 Gbps in point-to-point configurations. System-level bandwidth depends on PCB layout and load capacitance.
Does SN74CBTLV3861PWR require external pull-up resistors on the OE pin?
Yes - to ensure a defined high-impedance state during power-up or power-down, OE must be tied to VCC through an external pull-up resistor. The minimum value is determined by the current-sinking capability of the driving source; TI recommends verifying against the driver's IOL rating to maintain VIH ≥ 2.0 V at VCC = 3.6 V. The SN74CBTLV3861PWR itself has no internal pull-up on OE.
Can SN74CBTLV3861PWR be used for analog signal switching?
Yes - the SN74CBTLV3861PWR is a passive FET-based switch with rail-to-rail analog capability. It passes signals from GND to VCC without distortion or level shifting, supporting DC-coupled analog paths such as audio, sensor, or reference voltage routing - provided signal amplitude stays within the absolute maximum ratings (−0.5 V to 4.6 V) and current remains below 128 mA per channel.
What is the thermal resistance (θJA) of SN74CBTLV3861PWR in its TSSOP-24 package?
The SN74CBTLV3861PWR in the PW (TSSOP-24) package has a specified junction-to-ambient thermal resistance (θJA) of 88°C/W under standard JEDEC conditions. This value assumes a 2-layer PCB with 1-in² copper pour; actual performance improves with enhanced thermal vias and internal ground/power planes. No heatsink is required for typical operation at ≤10 µA ICC and ≤128 mA channel current.
Is SN74CBTLV3861PWR pin-compatible with other members of the CBTLV family?
No - the SN74CBTLV3861PWR has a unique 10-bit flow-through pinout (A1–A10 left side, B1–B10 right side) incompatible with 8-bit variants like SN74CBTLV3245PWR (which uses interleaved A/B pins). While both use TSSOP-24, direct replacement would require PCB redesign due to differing pin assignments and terminal grouping. Always verify pin mapping using the official TI package drawings for SN74CBTLV3861PWR.
SN74CBTLV3861PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTLV
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 10 x 1:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2.3V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
SN74CBTLV3861PWR FAQ
1.How can I place an order for SN74CBTLV3861PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74CBTLV3861PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74CBTLV3861PWR reliable?
The price and inventory of SN74CBTLV3861PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTLV3861PWR is usually 5 days.
3.What payment methods are accepted for SN74CBTLV3861PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74CBTLV3861PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74CBTLV3861PWR?
SN74CBTLV3861PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74CBTLV3861PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74CBTLV3861PWR?
For technical support, including SN74CBTLV3861PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTLV3861PWR requirements.
6.How does Aetrix verify that SN74CBTLV3861PWR is sourced from the original manufacturer or authorized distributors?
All SN74CBTLV3861PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTLV3861PWR meets industry standards.
7.What is the process for return or replacement of SN74CBTLV3861PWR?
All SN74CBTLV3861PWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTLV3861PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTLV3861PWR part is unused and in its original packaging.
Return procedure for SN74CBTLV3861PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74CBTLV3861PWR Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

