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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74CBTR16861DGVR

Name: SN74CBTR16861DGVR
Brand: Texas Instruments
SKU: SN74CBTR16861DGVR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74CBTR16861DGVR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 48-TFSOP (0.173", 4.40mm Width)

Datasheet:: SN74CBTR16861DGVR.pdf

Description:: IC BUS SWITCH 10 X 1:1 48TVSOP

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Product details

Overview

SN74CBTR16861DGVR from Texas Instruments is a 20-bit FET bus switch organized as two independent 10-bit switches with separate OE controls, featuring 25-Ω on-state resistance, TTL-compatible input levels, and operation from –40°C to 85°C. It enables high-speed bidirectional signal routing in memory expansion and data-path isolation applications with minimal propagation delay (1.25 ns typical) and integrated noise-reduction series resistance.

For engineers reviewing the SN74CBTR16861DGVR datasheet, SN74CBTR16861DGVR pinout, SN74CBTR16861DGVR application, or SN74CBTR16861DGVR equivalent, key selection criteria include its dual 10-bit channel architecture, 25-Ω r_on, 5-V supply compatibility, 48-pin TVSOP package, and latch-up immunity exceeding 100 mA per JESD 78 Class II.

Technical Context

The SN74CBTR16861DGVR implements two independent 10-bit FET-based analog switches controlled by dedicated OE inputs-each enabling low-impedance connection between A and B ports when asserted low. Its 25-Ω nominal on-resistance is matched across channels and stable over voltage and temperature, supporting clean signal integrity without external termination.

It operates with TTL-level control inputs (V_IL ≤ 0.8 V, V_VIH ≥ 2 V) while powered from a single 4–5.5 V supply, and integrates ESD protection exceeding 2000-V HBM and 200-V MM. The device exhibits low dynamic power consumption (3 µA I_CC) and fast enable/disable timing (t_en = 2.7–9 ns, t_dis = 2.3–6.9 ns).

Key Specifications

Parameter	Value and Actual Design Meaning
Switch Type	20-bit dual 10-bit FET bus switch with independent OE control per 10-bit section
On-State Resistance (r_on)	20–48 Ω typical at V_CC = 4–5.5 V; ensures minimal voltage drop and signal attenuation
Propagation Delay (t_pd)	1.25 ns typical at V_CC = 4 V or 5 V; supports high-speed parallel data paths up to ~400 MHz
Supply Voltage Range	4 V to 5.5 V; compatible with standard 5-V logic systems and tolerant of 5% rail variation
ESD Protection	2000-V HBM (JESD22-A114), 200-V MM (JESD22-A115); reduces need for external protection circuitry
Latch-Up Immunity	>100 mA per JESD 78 Class II; prevents destructive latch-up under transient overcurrent conditions
Operating Temperature	–40°C to +85°C; qualified for industrial-grade embedded and computing environments

Pinout & Package

SN74CBTR16861DGVR is housed in a 48-pin TVSOP (DGV) package measuring 7.7 mm × 4.4 mm × 1.2 mm, with 0.4 mm pitch and JEDEC MO-153 compliance. The package features exposed pad-less construction and moisture sensitivity level (MSL) 1 rating for unlimited floor life at ≤30°C/60% RH.

Pin/Terminal	Circuit Role	Design Meaning
1A1–1A10, 2A1–2A10	Input/Output Port A (Channel Group 1 & 2)	10-bit bidirectional signal terminals for first and second 10-bit switch sections
1B1–1B10, 2B1–2B10	Input/Output Port B (Channel Group 1 & 2)	Corresponding 10-bit bidirectional terminals connected to A ports when OE is active low
1OE, 2OE	Output Enable (Active-Low)	Independent control inputs enabling/disabling each 10-bit switch section; OE = L connects A↔B
VCC	Power Supply	Single 4–5.5 V supply for internal FET bias and level translation; decoupling required near pins 25 & 47
GND	Ground Reference	Two dedicated ground pins (pins 12 & 24) minimize ground bounce in high-speed switching
NC	No Internal Connection	Pins 1, 11, 22, 48 are unconnected; must be left floating or tied to GND per layout best practice

Key Features

Feature	Design Value
25-Ω matched on-resistance	Reduces signal reflection and eliminates need for external 25–50 Ω termination resistors on PCB traces
Dual independent 10-bit control	Enables selective isolation of two distinct data buses (e.g., CPU address/data vs. peripheral interface) with no shared timing constraints
TTL-compatible control inputs	Accepts standard 0.8 V / 2.0 V logic thresholds directly from 5-V microcontrollers or FPGAs without level shifters
Low 1.25 ns propagation delay	Maintains timing margins in 100+ MHz parallel bus systems such as SRAM expansion or FPGA I/O bridging
High ESD and latch-up robustness	Supports handling and board-level reliability in automated assembly and industrial field environments without added protection

Applications

Memory Expansion Interface	PCI/ISA Bus Isolation
Use Scenario: Expanding local memory capacity in microcontroller-based systems using external SRAM or Flash devices. IC Role / Device Role / Timing Role: Bidirectional 20-bit data/address bus switch that isolates memory subsystem during CPU idle cycles or DMA transfers. Use Value: Enables zero-wait-state access with 1.25 ns delay and 25-Ω r_on, preserving signal integrity across 10-cm PCB traces without termination.	Use Scenario: Electrically isolating legacy PCI or ISA bus segments to prevent contention during hot-swap or configuration changes. IC Role / Device Role / Timing Role: High-speed analog switch providing galvanic separation between bus masters while maintaining full 33-MHz timing compliance. Use Value: Dual 10-bit control allows independent enable/disable of address and data lanes, reducing bus turnaround latency by >3 ns versus discrete solutions.
FPGA I/O Bridging	Test Access Port Multiplexing
Use Scenario: Interfacing multiple FPGA I/O banks operating at different voltage levels or timing domains to a common test/debug bus. IC Role / Device Role / Timing Role: Level-agnostic bidirectional switch translating signals between 3.3-V and 5-V logic domains without direction control pins. Use Value: TTL-compatible inputs and 4–5.5 V V_CC tolerance allow direct connection to both 3.3-V and 5-V FPGA I/O, simplifying mixed-voltage board design.	Use Scenario: Sharing a single JTAG or boundary-scan controller across multiple ASICs or SoCs on a production test fixture. IC Role / Device Role / Timing Role: Low-capacitance (5 pF C_io(OFF)) multiplexer routing TCK/TMS/TDI/TDO signals to selected DUT without skew or loading degradation. Use Value: 5 pF off-state capacitance minimizes signal distortion at 25-MHz JTAG clock rates, ensuring reliable IEEE 1149.1 compliance across 10+ DUTs.

Memory Expansion Interface

PCI/ISA Bus Isolation

Use Scenario: Expanding local memory capacity in microcontroller-based systems using external SRAM or Flash devices.

IC Role / Device Role / Timing Role: Bidirectional 20-bit data/address bus switch that isolates memory subsystem during CPU idle cycles or DMA transfers.

Use Value: Enables zero-wait-state access with 1.25 ns delay and 25-Ω r_on, preserving signal integrity across 10-cm PCB traces without termination.

Use Scenario: Electrically isolating legacy PCI or ISA bus segments to prevent contention during hot-swap or configuration changes.

IC Role / Device Role / Timing Role: High-speed analog switch providing galvanic separation between bus masters while maintaining full 33-MHz timing compliance.

Use Value: Dual 10-bit control allows independent enable/disable of address and data lanes, reducing bus turnaround latency by >3 ns versus discrete solutions.

FPGA I/O Bridging

Test Access Port Multiplexing

Use Scenario: Interfacing multiple FPGA I/O banks operating at different voltage levels or timing domains to a common test/debug bus.

IC Role / Device Role / Timing Role: Level-agnostic bidirectional switch translating signals between 3.3-V and 5-V logic domains without direction control pins.

Use Value: TTL-compatible inputs and 4–5.5 V V_CC tolerance allow direct connection to both 3.3-V and 5-V FPGA I/O, simplifying mixed-voltage board design.

Use Scenario: Sharing a single JTAG or boundary-scan controller across multiple ASICs or SoCs on a production test fixture.

IC Role / Device Role / Timing Role: Low-capacitance (5 pF C_io(OFF)) multiplexer routing TCK/TMS/TDI/TDO signals to selected DUT without skew or loading degradation.

Use Value: 5 pF off-state capacitance minimizes signal distortion at 25-MHz JTAG clock rates, ensuring reliable IEEE 1149.1 compliance across 10+ DUTs.

Equivalent & Alternatives

The following parts are listed as comparable options for similar FET bus switch applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74CBT16210DGVR	10-bit (not 20-bit), identical 25-Ω r_on, same TVSOP-24 package; lacks dual-OE architecture	Suitable only for half-width data paths; requires two units for full 20-bit coverage, increasing board area and routing complexity	Select when 10-bit granularity suffices and space permits dual placement; not a drop-in replacement for SN74CBTR16861DGVR
SN74CBTLV16861DGVR	20-bit, 3.3-V only (2.3–3.6 V), lower r_on (12 Ω typ), same pinout but incompatible V_CC range	Designed for low-voltage systems; cannot operate at 5 V and risks damage if supplied above 3.6 V	Choose for 3.3-V-only designs requiring lower r_on; requires full power-rail redesign to replace SN74CBTR16861DGVR in 5-V systems

Compared with SN74CBTR16861DGVR, SN74CBT16210DGVR halves channel count and increases system component count, while SN74CBTLV16861DGVR mandates strict 3.3-V operation-neither offers pin-compatible 5-V 20-bit switching with dual OE control.

Availability

SN74CBTR16861DGVR is available at Aetrix Electronics and suitable for memory expansion interfaces, PCI bus isolation, FPGA I/O bridging, and JTAG test access port multiplexing requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant green packaging.

Supply support for SN74CBTR16861DGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and logic solutions with emphasis on reliability, industrial qualification, and broad portfolio scalability.

The SN74CBTR16861DGVR belongs to TI's Widebus™ family of high-speed bus switches, engineered specifically for low-latency, low-noise signal routing in 5-V computing, communications, and industrial control systems.

FAQ

What is the maximum continuous current per channel for the SN74CBTR16861DGVR?

The SN74CBTR16861DGVR supports a continuous channel current of 128 mA per switch path, as specified in its absolute maximum ratings. This rating applies under recommended operating conditions (V_CC = 4–5.5 V, T_A = –40°C to 85°C) and ensures safe conduction without thermal runaway or parametric shift. Exceeding this current may degrade r_on stability or trigger latch-up.

Does the SN74CBTR16861DGVR require external pull-up or pull-down resistors on its OE inputs?

No, the SN74CBTR16861DGVR does not require external pull-up or pull-down resistors on its OE inputs. Its TTL-compatible input thresholds (V_IL ≤ 0.8 V, V_IH ≥ 2 V) allow direct connection to 5-V logic outputs. However, TI recommends tying all unused control inputs to V_CC or GND to prevent floating states that could cause unintended switching or increased ICC.

Can the SN74CBTR16861DGVR be used with 3.3-V logic signals while powered at 5 V?

Yes, the SN74CBTR16861DGVR accepts 3.3-V logic signals on its A/B ports and OE inputs when powered at 5 V. Its input voltage range is –0.5 V to 7 V, and it maintains TTL-compatible thresholds regardless of V_CC. Signal translation occurs passively through the FET channel, preserving waveform fidelity without level-shifting circuitry.

What is the off-state capacitance (C_io(OFF)) of the SN74CBTR16861DGVR and why does it matter?

The off-state capacitance of the SN74CBTR16861DGVR is 5 pF maximum, measured at VO = 3 V or 0 V with OE = V_CC. This low value minimizes capacitive loading on driven nets during disable, preserving signal edge rates and reducing crosstalk in high-density parallel buses-critical for maintaining setup/hold timing in 100+ MHz memory interfaces.

Is the SN74CBTR16861DGVR pin-compatible with other members of the Widebus™ 20-bit switch family?

Yes, the SN74CBTR16861DGVR shares identical 48-pin TVSOP (DGV) pinout with SN74CBTLV16861DGVR and SN74CBT16861DGVR, including matching A/B port assignments, OE locations, and power/ground pin positions. However, electrical differences-including supply voltage range, r_on, and ESD rating-require validation before substitution in existing designs.

SN74CBTR16861DGVR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74CBTR

Package/Case:: 48-TFSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Type:: Bus Switch

Circuit:: 10 x 1:1

Independent Circuits:: 2

Current - Output High, Low:: -

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 48-TVSOP

SN74CBTR16861DGVR FAQ

1.How can I place an order for SN74CBTR16861DGVR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74CBTR16861DGVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74CBTR16861DGVR reliable?

The price and inventory of SN74CBTR16861DGVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74CBTR16861DGVR is usually 5 days.

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SN74CBTR16861DGVR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74CBTR16861DGVR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74CBTR16861DGVR?

For technical support, including SN74CBTR16861DGVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74CBTR16861DGVR requirements.

6.How does Aetrix verify that SN74CBTR16861DGVR is sourced from the original manufacturer or authorized distributors?

All SN74CBTR16861DGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74CBTR16861DGVR meets industry standards.

7.What is the process for return or replacement of SN74CBTR16861DGVR?

All SN74CBTR16861DGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTR16861DGVR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74CBTR16861DGVR part is unused and in its original packaging.

Return procedure for SN74CBTR16861DGVR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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