Texas Instruments SN74CBTS3384PWR
- Part No.:
- SN74CBTS3384PWR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 24-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74CBTS3384PWR.pdf
- Description:
- IC BUS SWITCH 5 X 1:1 24TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,000
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Product details
Overview
SN74CBTS3384PWR from Texas Instruments is a 10-bit FET bus switch with Schottky diode clamping, designed for high-speed TTL-compatible signal routing in memory and data-path applications. It features 5-Ω on-state resistance, 0.25 ns typical propagation delay at 5 V, and dual independent 5-bit channels controlled by separate OE inputs. Used in address/data bus isolation for microcontrollers and FPGAs operating from –40°C to 85°C.
For engineers reviewing the SN74CBTS3384PWR datasheet, SN74CBTS3384PWR pinout, SN74CBTS3384PWR application, or SN74CBTS3384PWR equivalent, key selection criteria include on-resistance matching, undershoot clamping capability, OE-controlled bidirectional switching, and TSSOP-24 thermal performance under 5-V operation.
Technical Context
The SN74CBTS3384PWR implements two independent 5-bit FET-based analog switches with TTL-compatible control logic and integrated Schottky clamps on all I/Os to suppress negative undershoot. Its low 5–7 Ω ron ensures minimal RC delay when driving 50-pF loads.
Each channel operates bidirectionally: when OE is low, A and B ports are connected; when OE is high, both ports enter high-impedance state. Control inputs accept 0.8 V/2.0 V TTL thresholds, and supply voltage range is 4 V to 5.5 V - no 3.3-V operation supported.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| On-state resistance (ron) | 5 Ω typical at VCC = 4.5 V, II = 30 mA - enables <0.35 ns propagation delay into 50-pF loads |
| Propagation delay (tpd) | 0.25 ns max at VCC = 5 V - supports >1 GHz signal routing without timing degradation |
| Supply voltage range | 4 V to 5.5 V - compatible only with 5-V TTL/CMOS systems; not 3.3-V tolerant |
| I/O undershoot clamping | Schottky diodes clamp to –0.6 V (A/B) and –1.2 V (control) - protects downstream logic from ESD-induced negative transients |
| Channel current rating | 128 mA continuous per switch - sufficient for driving multiple CMOS inputs or short PCB traces |
| Input capacitance (Ci) | 6 pF per control input - minimizes loading on upstream drivers and preserves signal edge integrity |
| Operating temperature | –40°C to +85°C - qualified for industrial-grade embedded control and instrumentation environments |
Pinout & Package
TSSOP-24 package (PW), 7.8 mm × 4.4 mm × 1.2 mm height, lead pitch 0.65 mm, RoHS-compliant NiPdAu finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 12, 13, 24 | OE (1OE, 2OE) | Active-low enable for respective 5-bit channel; drives high-Z state when high |
| 2–6, 14–18 | 1B1–1B5, 2B1–2B5 | Bi-directional I/O port B terminals; internally clamped with Schottky diodes |
| 3–7, 15–19 | 1A1–1A5, 2A1–2A5 | Bi-directional I/O port A terminals; identical clamping and ron as B-side |
| 11, 22 | GND | Power ground reference for switch body and clamp diodes |
| 23 | VCC | Positive supply (4–5.5 V); powers internal FETs and clamp circuitry |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional 5-Ω analog switch | Enables transparent, low-distortion signal pass-through between A and B ports without direction control logic |
| Integrated Schottky clamping | Prevents I/O undershoot below –0.6 V, eliminating need for external protection diodes in noisy bus environments |
| Dual independent OE controls | Allows selective isolation of two 5-bit data groups - e.g., address vs. data lines - without shared timing constraints |
| TTL-compatible input thresholds | Accepts standard 0.8 V / 2.0 V logic levels - interoperable with legacy 5-V microcontrollers and ASICs |
| Low 6-pF input capacitance | Reduces capacitive loading on upstream drivers, preserving rise/fall times in high-speed parallel interfaces |
Applications
| Memory Bus Isolation | FPGA I/O Expansion |
|---|---|
|
Use Scenario: Isolating SRAM or Flash memory address/data buses from CPU during power-down or reset sequences. IC Role / Device Role / Timing Role: Bidirectional analog switch enabling/disabling signal paths with sub-nanosecond delay and zero hold-time impact. Use Value: Prevents back-driving and contention on shared memory buses while maintaining full 5-V signal integrity. |
Use Scenario: Expanding FPGA I/O count by routing signals through external logic banks or peripheral interfaces. IC Role / Device Role / Timing Role: Low-ron bus switch providing glitch-free signal extension without added setup/hold overhead. Use Value: Enables FPGA pin multiplexing without degrading timing margins - critical for DDR2/SDRAM co-simulation paths. |
| Microcontroller Peripheral Multiplexing | Legacy System Bus Bridging |
|
Use Scenario: Sharing UART, SPI, or GPIO pins between multiple peripherals using software-controlled OE signals. IC Role / Device Role / Timing Role: Dual-channel switch allowing dynamic reconfiguration of 10-bit I/O groups under firmware control. Use Value: Eliminates need for discrete MOSFET arrays or complex CPLD glue logic in space-constrained MCU designs. |
Use Scenario: Interfacing modern 5-V logic to legacy ISA or PC/104 bus architectures with mixed-voltage signaling. IC Role / Device Role / Timing Role: Voltage-level agnostic analog switch supporting bidirectional data flow across heterogeneous subsystems. Use Value: Maintains signal fidelity across bus bridges where level shifters would introduce unacceptable skew or latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74CBT3384PWR | Omits Schottky clamping; higher VIK (–0.5 V); otherwise identical pinout and ron | Not suitable for systems exposed to significant ground bounce or ESD events on I/O lines | Select SN74CBT3384PWR only if board-level clamping is already implemented and cost reduction is prioritized. |
| SN74LVC1G3157DCKR | Single-channel SPDT, 3.3-V only, 6-Ω ron, no integrated clamping, SC70-6 package | Limited to point-to-point switching; requires external level translation for 5-V interface compatibility | Use only for low-pin-count, 3.3-V-only designs where space is critical and bus isolation is not required. |
Compared with SN74CBTS3384PWR, SN74CBT3384PWR reduces system protection margin but lowers BOM cost, while SN74LVC1G3157DCKR trades channel count and voltage compatibility for footprint reduction - neither offers drop-in replacement capability.
Availability
SN74CBTS3384PWR is available at Aetrix Electronics and suitable for memory bus isolation, FPGA I/O expansion, and microcontroller peripheral multiplexing requiring stable component supply across industrial temperature ranges.
Supply support for SN74CBTS3384PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 90 years of innovation in industrial, automotive, and communications markets.
The SN74CBTS3384PWR belongs to TI's CBTS family of high-speed bus switches, engineered specifically for low-latency, bidirectional signal routing in 5-V digital systems with robust noise immunity.
FAQ
Is SN74CBTS3384PWR compatible with 3.3-V logic systems?
No, SN74CBTS3384PWR is not 3.3-V compatible. Its recommended operating supply is 4 V to 5.5 V, and its control inputs require TTL thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V) referenced to VCC. Driving OE or I/Os from 3.3-V sources may result in undefined switching behavior or increased ICC leakage. For 3.3-V systems, consider level-shifting circuitry or alternate families such as LVC.
What is the maximum load capacitance SN74CBTS3384PWR can drive while maintaining specified tpd?
The SN74CBTS3384PWR's 0.25 ns propagation delay is characterized at CL = 50 pF. While it can drive higher capacitances, delay increases linearly with load (tpd ≈ ron × CL). For example, at 100 pF, expected tpd exceeds 0.5 ns. Keep total trace + stub + receiver capacitance ≤50 pF for guaranteed timing compliance in high-speed bus applications.
Does SN74CBTS3384PWR support hot insertion or live bus swapping?
No, SN74CBTS3384PWR does not support hot insertion. Its absolute maximum ratings specify VI down to –0.5 V, but the integrated Schottky clamps only protect against transient undershoot-not sustained negative bias. Applying voltage to A/B ports before VCC stabilization risks latch-up or permanent damage. Power sequencing must follow VCC-first, then signal application.
Can both OE inputs be tied together and driven by a single controller signal?
Yes, SN74CBTS3384PWR allows tying 1OE and 2OE together for synchronous control of all 10 bits. However, doing so eliminates independent channel isolation - both 5-bit groups will switch simultaneously. This configuration is valid for applications like global bus enable/disable but forfeits the device's dual-OE flexibility for partial bus gating.
What is the thermal resistance (θJA) of SN74CBTS3384PWR in its TSSOP-24 package?
The SN74CBTS3384PWR in TSSOP-24 (PW) package has a specified junction-to-ambient thermal resistance (θJA) of 88°C/W under JEDEC JESD 51-7 conditions. With typical ICC < 3 µA and ron-dominated power dissipation, self-heating remains negligible at normal operating currents - no heatsinking is required even at full 128-mA per channel.
SN74CBTS3384PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74CBTS
- Package/Case:
- 24-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Bus Switch
- Circuit:
- 5 x 1:1
- Independent Circuits:
- 2
- Current - Output High, Low:
- -
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-TSSOP
SN74CBTS3384PWR FAQ
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7.What is the process for return or replacement of SN74CBTS3384PWR?
All SN74CBTS3384PWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74CBTS3384PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74CBTS3384PWR part is unused and in its original packaging.
Return procedure for SN74CBTS3384PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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