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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74F138D

Name: SN74F138D
Brand: Texas Instruments
SKU: SN74F138D
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74F138D

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74F138D.pdf

Description:: IC DECODER/DEMUX 1X3:8 16SOIC

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Product details

Overview

SN74F138D from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC designed for high-speed memory decoding and data routing. It features three enable inputs (G1, G2A, G2B), eight active-low decoded outputs (Y0–Y7), propagation delays as low as 2.7 ns (tPLH) at VCC = 5 V, and operates over 0°C to 70°C. It is used in address decoding for SRAM/ROM systems where minimal added system delay is critical.

For engineers reviewing the SN74F138D datasheet, SN74F138D pinout, SN74F138D application, or SN74F138D equivalent, key selection criteria include enable-input logic configuration (two active-low, one active-high), output drive capability (20 mA sink), TTL-compatible voltage thresholds, and SOIC-16 package compatibility with legacy 74F logic layouts.

Technical Context

The SN74F138D implements combinational logic decoding using standard TTL circuitry with Schottky-clamped transistors for speed. Its three binary select inputs (A, B, C) and three enable inputs (G1, G2A, G2B) fully determine output state per the function table - only one Yx output goes low when all enables are satisfied. No internal latching or clocking is present; operation is purely level-sensitive and asynchronous.

Cascading is supported via enable-input chaining: G2A/G2B can accept inverted outputs from upstream decoders, while G1 serves as a global enable or data input for demultiplexing. The device does not include on-chip inverters for select lines - external inversion is required only when expanding beyond 8 outputs without logic gates.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage (VCC)	4.5 V to 5.5 V - ensures compatibility with standard 5 V TTL bus systems and stable operation under rail variation.
Propagation Delay (tPLH/tPHL)	2.7 ns to 9 ns - enables use in sub-100 MHz address decode paths without adding measurable latency to memory access timing.
Output Drive (IOL)	20 mA sink per output - sufficient to directly drive multiple TTL inputs or small LED indicators without buffering.
Input Thresholds (VIH/VIL)	VIH = 2.0 V min, VIL = 0.8 V max - guarantees reliable recognition of standard TTL logic levels across temperature and voltage corners.
Operating Temperature	0°C to 70°C - qualifies for commercial-grade embedded control, industrial I/O, and test equipment applications.
Package	SOIC-16 (D package) - surface-mount footprint compatible with automated assembly and PCB space-constrained designs.

Pinout & Package

SN74F138D is housed in a 16-pin Small-Outline Integrated Circuit (SOIC) package with 1.27 mm pitch, 10.0–10.4 mm body width, and maximum 2.00 mm height. Pin 1 is marked by a beveled corner or notch; leads are gull-wing shaped for reflow soldering.

Pin/Terminal	Circuit Role	Design Meaning
1 (A)	Binary Select Input	LSB of 3-bit address; tied low/high to select specific output line in conjunction with B and C.
2 (B)	Binary Select Input	Mid-bit of 3-bit address; determines output group (Y0–Y3 vs Y4–Y7) when A and C are fixed.
3 (C)	Binary Select Input	MSB of 3-bit address; primary determinant of upper/lower half of output set.
4 (G2A)	Active-Low Enable Input	Must be low to allow decoding; used for hierarchical enable chaining in multi-chip address maps.
5 (G2B)	Active-Low Enable Input	Second active-low enable; combined with G2A to reduce external gate count during cascading.
6 (G1)	Active-High Enable Input	Global enable or data input for demux mode; when used as data line, outputs mirror inverted select pattern.
7 (Y0)	Active-Low Output	Low when A=B=C=0 and all enables active; drives memory chip-select or peripheral enable signals.
8 (GND)	Ground Reference	Power return path for all internal logic and output stages; must be low-impedance for noise immunity.
9 (Y1)	Active-Low Output	Low when A=1, B=C=0; provides dedicated decode for second memory bank or I/O register.
10 (Y2)	Active-Low Output	Low when A=0, B=1, C=0; supports interleaved addressing schemes in dual-bank memory controllers.
11 (Y3)	Active-Low Output	Low when A=B=1, C=0; commonly assigned to boot ROM or configuration EEPROM select.
12 (Y4)	Active-Low Output	Low when A=0, B=C=1; used for expansion I/O or secondary peripheral mapping.
13 (Y5)	Active-Low Output	Low when A=1, B=0, C=1; supports dynamic address remapping in real-time control systems.
14 (Y6)	Active-Low Output	Low when A=0, B=1, C=1; often tied to interrupt controller or DMA channel enable.
15 (Y7)	Active-Low Output	Low when A=B=C=1; typically reserved for highest-priority device or diagnostic mode activation.
16 (VCC)	Positive Supply	+5 V power rail; bypass capacitor (0.1 µF) required near pin for transient current stability.

Key Features

Feature	Design Value
Three Enable Inputs	G1 (active-high), G2A/G2B (active-low) simplify hierarchical decoding without external inverters - enables 24-line expansion with zero added gates.
High-Speed Propagation	Typical tPLH = 5.2 ns at VCC = 5 V - ensures decoder delay remains below typical 15 ns SRAM access time, preserving system timing margins.
Active-Low Outputs	All eight Yx outputs assert low on selection - directly interfaces with common active-low chip-select (/CS) and output-enable (/OE) pins on memory and peripherals.
TTL-Compatible Interface	VIH = 2.0 V, VIL = 0.8 V, IOL = 20 mA - interoperates seamlessly with legacy 74LS, 74S, and other F-series logic without level-shifting.
Demultiplexing Capability	G1 accepts data input while A/B/C act as address lines - converts 1-bit serial data + 3-bit address into 1-of-8 parallel outputs.

Applications

Memory Address Decoding	Peripheral Device Selection
Use Scenario: Decoding 13-bit address bus to select one of eight 8K×8 SRAM chips in a microcontroller-based data logger. IC Role / Device Role / Timing Role: SN74F138D acts as the primary address decoder, asserting /CS on exactly one memory chip per 3-bit segment (A0–A2), minimizing address setup/hold overhead. Use Value: Propagation delay ≤8.5 ns ensures total decode + memory access remains within 35 ns cycle budget, enabling 25 MHz bus operation.	Use Scenario: Selecting among eight UART, SPI, or GPIO expansion ICs connected to an FPGA I/O header. IC Role / Device Role / Timing Role: SN74F138D routes control signals to individual peripheral ICs using FPGA-configurable A/B/C and enable lines, isolating communication channels. Use Value: Active-low outputs match standard /EN pins on most interface ICs, eliminating need for discrete inverters and reducing BOM count by up to 8 parts.
Industrial I/O Multiplexing	Legacy System Bus Expansion
Use Scenario: Distributing single digital control signal (e.g., reset or watchdog pulse) to eight independent PLC modules. IC Role / Device Role / Timing Role: SN74F138D functions as a synchronous demultiplexer: G1 carries the pulse, A/B/C select target module, outputs trigger module-specific reset latches. Use Value: 20 mA output drive allows direct connection to module reset inputs without buffer transistors, simplifying field-replaceable board design.	Use Scenario: Adding two additional 16K memory banks to a vintage 8086-based computer using existing 74F logic architecture. IC Role / Device Role / Timing Role: SN74F138D replaces discrete NAND/NOR gate networks in original schematics, restoring full 1-MB address space with identical timing behavior. Use Value: Pinout and DC specs match original 74F138 design - no PCB redesign or firmware changes needed for drop-in replacement.

Memory Address Decoding

Peripheral Device Selection

Use Scenario: Decoding 13-bit address bus to select one of eight 8K×8 SRAM chips in a microcontroller-based data logger.

IC Role / Device Role / Timing Role: SN74F138D acts as the primary address decoder, asserting /CS on exactly one memory chip per 3-bit segment (A0–A2), minimizing address setup/hold overhead.

Use Value: Propagation delay ≤8.5 ns ensures total decode + memory access remains within 35 ns cycle budget, enabling 25 MHz bus operation.

Use Scenario: Selecting among eight UART, SPI, or GPIO expansion ICs connected to an FPGA I/O header.

IC Role / Device Role / Timing Role: SN74F138D routes control signals to individual peripheral ICs using FPGA-configurable A/B/C and enable lines, isolating communication channels.

Use Value: Active-low outputs match standard /EN pins on most interface ICs, eliminating need for discrete inverters and reducing BOM count by up to 8 parts.

Industrial I/O Multiplexing

Legacy System Bus Expansion

Use Scenario: Distributing single digital control signal (e.g., reset or watchdog pulse) to eight independent PLC modules.

IC Role / Device Role / Timing Role: SN74F138D functions as a synchronous demultiplexer: G1 carries the pulse, A/B/C select target module, outputs trigger module-specific reset latches.

Use Value: 20 mA output drive allows direct connection to module reset inputs without buffer transistors, simplifying field-replaceable board design.

Use Scenario: Adding two additional 16K memory banks to a vintage 8086-based computer using existing 74F logic architecture.

IC Role / Device Role / Timing Role: SN74F138D replaces discrete NAND/NOR gate networks in original schematics, restoring full 1-MB address space with identical timing behavior.

Use Value: Pinout and DC specs match original 74F138 design - no PCB redesign or firmware changes needed for drop-in replacement.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS138N	Slower propagation (15–25 ns), lower IOL (8 mA), same pinout and logic function.	Suitable for non-critical timing systems where power consumption < 20 mW is prioritized over speed.	Select when board-level timing margin exceeds 20 ns and legacy LS-family sourcing is preferred.
SN74HC138DR	CMOS technology, wider VCC range (2–6 V), higher noise immunity, but requires 3.3 V or 5 V supply and has different input thresholds.	Better for mixed-voltage systems or battery-powered devices needing lower static current (< 8 µA).	Choose for new designs targeting 3.3 V domains or requiring reduced power; verify level compatibility with driving logic.

Compared with SN74LS138N, SN74F138D delivers 3× faster decoding with 2.5× stronger output drive, making it preferable for high-throughput memory subsystems; versus SN74HC138DR, it offers guaranteed TTL interoperability and tighter propagation skew but lacks CMOS-level power efficiency.

Availability

SN74F138D is available at Aetrix Electronics and suitable for industrial control panels, legacy computing upgrades, and test instrumentation requiring stable component supply and long-term obsolescence management.

Supply support for SN74F138D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and aerospace qualification.

The SN74F138D belongs to TI's 74F family of fast TTL logic devices, engineered specifically for high-speed memory decoding and data-routing applications where propagation delay and output drive are critical.

FAQ

What is the maximum operating frequency supported by SN74F138D?

The SN74F138D is not a clocked device and has no defined maximum operating frequency. Its performance is governed by propagation delay: with tPHL/tPLH ≤ 9 ns, it supports address decode cycles up to approximately 110 MHz in ideal conditions. Real-world system frequency depends on board layout, load capacitance, and driving source rise/fall times - always validate timing in the final design using worst-case delay values from the datasheet.

Can SN74F138D be used as a demultiplexer, and how is that configured?

Yes, SN74F138D can operate as a 1-to-8 demultiplexer. Configure G1 as the data input (high = pass, low = block), and use A, B, C as the 3-bit select address. When G1 is high and the enable condition is met (G2A = G2B = low), the selected Yx output mirrors the inverse of G1 - so a high G1 produces a low Yx. This allows serial data distribution across eight parallel paths without additional logic.

Does SN74F138D require external pull-up resistors on its outputs?

No, SN74F138D does not require external pull-up resistors. Its outputs are active-low, Totem-Pole TTL drivers capable of sinking 20 mA (IOL) and sourcing –1 mA (IOH). When an output is inactive (high), the internal pull-up transistor provides sufficient drive to maintain a valid TTL high level (~3.4 V at VCC = 4.5 V); pull-ups are only needed if interfacing with open-collector loads or non-TTL receivers.

Is SN74F138D pin-compatible with SN74LS138?

Yes, SN74F138D is pin-compatible with SN74LS138 in the same package (e.g., SOIC-16 or PDIP-16). Both share identical pin assignments, logic function, and enable/input/output configurations. However, SN74F138D offers faster propagation, higher output drive, and greater input noise margin - making it a direct functional upgrade where timing or loading demands exceed LS-family capabilities.

What is the meaning of "NC" pins on SN74F138D, and should they be connected?

"NC" stands for "No internal connection." On SN74F138D in SOIC-16 (D package), pins 3, 5, 6, and 13 are NC - they are physically present but unconnected to die circuitry. These pins must remain unconnected (floating) and should never be tied to VCC, GND, or signals. Doing so may cause mechanical stress or unintended coupling; leave them unpopulated or route traces away from these pads per TI's layout guidelines.

SN74F138D Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74F

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Type:: Decoder/Demultiplexer

Circuit:: 1 x 3:8

Independent Circuits:: 1

Current - Output High, Low:: 1mA, 20mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: 0°C ~ 70°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74F138D FAQ

1.How can I place an order for SN74F138D through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74F138D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74F138D reliable?

The price and inventory of SN74F138D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74F138D is usually 5 days.

3.What payment methods are accepted for SN74F138D?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74F138D transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74F138D?

SN74F138D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74F138D order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74F138D?

For technical support, including SN74F138D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74F138D requirements.

6.How does Aetrix verify that SN74F138D is sourced from the original manufacturer or authorized distributors?

All SN74F138D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74F138D meets industry standards.

7.What is the process for return or replacement of SN74F138D?

All SN74F138D units undergo pre-shipment inspection (PSI). If there is an issue with SN74F138D, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74F138D part is unused and in its original packaging.

Return procedure for SN74F138D:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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