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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74F138DR

Name: SN74F138DR
Brand: Texas Instruments
SKU: SN74F138DR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74F138DR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74F138DR.pdf

Description:: IC DECODER/DEMUX 1X3:8 16SOIC

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Product details

Overview

SN74F138DR from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC designed for high-speed memory decoding and data routing. It features three enable inputs (G1, G2A, G2B), eight active-low decoded outputs (Y0–Y7), propagation delays as low as 2.7 ns (tPLH), operates at VCC = 4.5–5.5 V, and is rated for 0°C to 70°C industrial temperature range. It is commonly used in address decoding for SRAM/ROM systems.

For engineers reviewing the SN74F138DR datasheet, SN74F138DR pinout, SN74F138DR application, or SN74F138DR equivalent, key selection considerations include its TTL-compatible input thresholds (VIH = 2 V, VIL = 0.8 V), 20 mA output sink capability, cascading support via dual active-low and one active-high enables, and SOIC-16 packaging for space-constrained PCB layouts.

Technical Context

The SN74F138DR implements positive-logic binary decoding with three select inputs (A, B, C) and three enable inputs (G1, G2A, G2B), where G2A and G2B are active-low and G1 is active-high. All outputs are active-low and open-collector compatible, enabling wired-OR expansion without external inverters.

Its architecture supports both decoding and demultiplexing modes: when used as a demultiplexer, one enable input (e.g., G1) serves as the data input while A/B/C control output selection. Cascading up to 24 lines requires no external inverters; 32-line expansion needs only one inverter.

Key Specifications

Parameter	Value and Actual Design Meaning
VCC Range	4.5 V to 5.5 V - Ensures compatibility with standard 5 V TTL logic rails and noise margin stability.
Propagation Delay (tPLH/tPHL)	2.7 ns to 9 ns - Enables use in high-speed memory systems where decoder delay must be negligible relative to memory access time.
Output Sink Current (IOL)	20 mA - Supports direct driving of multiple TTL inputs or LED indicators without external buffers.
Input Thresholds (VIH/VIL)	VIH = 2 V, VIL = 0.8 V - Matches standard TTL voltage levels for seamless interfacing with legacy 74-series logic.
Operating Temperature	0°C to 70°C - Qualified for commercial/industrial embedded applications, not extended or military grade.
Package	SOIC-16 (D package) - Surface-mount, RoHS-compliant, 16-pin small-outline IC with 1.27 mm pitch and tape-and-reel delivery (2500 pcs/reel).

Pinout & Package

SN74F138DR is housed in a 16-pin SOIC (Small Outline Integrated Circuit) package, 3.9 mm wide, 9.9 mm long, and 1.75 mm maximum height per TI NS0016A outline. Pin 1 is located at the top-left corner with notch or mark indicator; leads are gull-wing, lead-free (NIPDAU), MSL Level-1.

Pin/Terminal	Circuit Role	Design Meaning
1 (A)	Binary Select Input	LSB of 3-bit address; determines output line selection along with B and C.
2 (B)	Binary Select Input	Mid-bit of 3-bit address; combined with A and C, selects one of eight outputs.
3 (C)	Binary Select Input	MSB of 3-bit address; completes 3-bit binary decode for Y0–Y7 activation.
4 (G2A)	Active-Low Enable	First enable input; all outputs forced high unless G2A = LOW (along with G2B and G1).
5 (G2B)	Active-Low Enable	Second enable input; reduces need for external inverters during cascading.
6 (G1)	Active-High Enable	Third enable input; used as data input in demultiplexer mode when A/B/C are fixed.
7 (Y0)	Active-Low Output	Decoded output corresponding to A=B=C=0; sinks current when enabled and selected.
8 (GND)	Ground Reference	Power return path for internal circuitry and output drivers; must be low-impedance.
9 (Y1)	Active-Low Output	Output for A=1,B=0,C=0; identical electrical specs to Y0–Y7.
10 (Y2)	Active-Low Output	Output for A=0,B=1,C=0; supports wired-OR bus expansion.
11 (Y3)	Active-Low Output	Output for A=1,B=1,C=0; shares same timing and drive strength as other Yx pins.
12 (Y4)	Active-Low Output	Output for A=0,B=0,C=1; usable in memory chip-select generation.
13 (Y5)	Active-Low Output	Output for A=1,B=0,C=1; maintains consistent VOL ≤ 0.5 V at IOL = 20 mA.
14 (Y6)	Active-Low Output	Output for A=0,B=1,C=1; compatible with TTL and LSTTL fan-out requirements.
15 (Y7)	Active-Low Output	Output for A=B=C=1; highest-order decoded line; same VOH ≥ 2.5 V at IOH = –1 mA.
16 (VCC)	Supply Voltage	+5 V power rail; bypass capacitor (0.1 µF) recommended near pin for noise suppression.

Key Features

Feature	Design Value
Three Enable Inputs	G1 (active-high), G2A/G2B (active-low) simplify hierarchical decoding and eliminate external gating for 24-line expansion.
High-Speed Propagation	Typical tPLH = 5.2 ns at VCC = 5 V, CL = 50 pF - ensures decoder delay does not bottleneck memory access cycles.
Open-Collector Outputs	All Y0–Y7 are active-low, open-collector - enables wired-OR bus structures and mixed-voltage interfacing via pull-up resistors.
TTL-Compatible Interface	VIH = 2 V, VIL = 0.8 V, IIL = –0.6 mA - guarantees interoperability with standard 74LS/74F logic families without level shifting.
Demultiplexer Functionality	One enable input (e.g., G1) acts as data channel while A/B/C route it to selected Yx output - adds flexibility beyond pure decoding.

Applications

Memory Address Decoding	Peripheral Device Selection
Use Scenario: Decoding 3-bit address bus to generate individual chip-select signals for eight 8K×8 SRAM chips in a 64 KB memory subsystem. IC Role / Device Role / Timing Role: SN74F138DR acts as a high-speed address decoder, accepting A0–A2 and three enables (e.g., from upper address bits and CPU control) to assert one of eight active-low CS lines. Use Value: Propagation delay ≤ 9 ns ensures CS assertion occurs well within typical 15 ns SRAM access window, eliminating wait states.	Use Scenario: Selecting among eight I/O peripheral devices (UARTs, ADCs, GPIO expanders) connected to a microcontroller's data/address bus. IC Role / Device Role / Timing Role: SN74F138DR functions as a peripheral selector, using address lines and control signals (e.g., RD/WR strobes) to activate only the targeted device's chip-enable input. Use Value: Active-low open-collector outputs allow shared interrupt or status bus with pull-up, reducing interconnect count and simplifying arbitration logic.
Data Routing in Bus Systems	Logic Signal Multiplexing
Use Scenario: Distributing a single serial data stream (e.g., UART TX) to one of eight destination nodes in a test instrumentation rack. IC Role / Device Role / Timing Role: SN74F138DR operates in demultiplexer mode: G1 = data input, A/B/C = channel address, Y0–Y7 = routed outputs. Use Value: Eliminates need for discrete transistors or additional logic gates; supports data rates up to ~100 Mbps given 9 ns max delay and 50 pF load.	Use Scenario: Consolidating eight independent control signals (e.g., reset, enable, clock-gate) onto a shared 3-wire bus using time-division multiplexing. IC Role / Device Role / Timing Role: SN74F138DR serves as a logic multiplexer: A/B/C select which signal passes through to a common output node (via wired-OR or external OR gate). Use Value: Reduces PCB trace count and connector pin count by 8:1; leverages built-in enable logic to gate signal paths synchronously.

Memory Address Decoding

Peripheral Device Selection

Use Scenario: Decoding 3-bit address bus to generate individual chip-select signals for eight 8K×8 SRAM chips in a 64 KB memory subsystem.

IC Role / Device Role / Timing Role: SN74F138DR acts as a high-speed address decoder, accepting A0–A2 and three enables (e.g., from upper address bits and CPU control) to assert one of eight active-low CS lines.

Use Value: Propagation delay ≤ 9 ns ensures CS assertion occurs well within typical 15 ns SRAM access window, eliminating wait states.

Use Scenario: Selecting among eight I/O peripheral devices (UARTs, ADCs, GPIO expanders) connected to a microcontroller's data/address bus.

IC Role / Device Role / Timing Role: SN74F138DR functions as a peripheral selector, using address lines and control signals (e.g., RD/WR strobes) to activate only the targeted device's chip-enable input.

Use Value: Active-low open-collector outputs allow shared interrupt or status bus with pull-up, reducing interconnect count and simplifying arbitration logic.

Data Routing in Bus Systems

Logic Signal Multiplexing

Use Scenario: Distributing a single serial data stream (e.g., UART TX) to one of eight destination nodes in a test instrumentation rack.

IC Role / Device Role / Timing Role: SN74F138DR operates in demultiplexer mode: G1 = data input, A/B/C = channel address, Y0–Y7 = routed outputs.

Use Value: Eliminates need for discrete transistors or additional logic gates; supports data rates up to ~100 Mbps given 9 ns max delay and 50 pF load.

Use Scenario: Consolidating eight independent control signals (e.g., reset, enable, clock-gate) onto a shared 3-wire bus using time-division multiplexing.

IC Role / Device Role / Timing Role: SN74F138DR serves as a logic multiplexer: A/B/C select which signal passes through to a common output node (via wired-OR or external OR gate).

Use Value: Reduces PCB trace count and connector pin count by 8:1; leverages built-in enable logic to gate signal paths synchronously.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder/demultiplexer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS138N	Slower propagation (15–25 ns), lower ICC (2 mA), same pinout and logic function.	Better suited for low-power, non-critical timing systems; not appropriate for sub-20 ns memory interfaces.	Select SN74LS138N only if speed is not constrained and power budget is tight; verify VIH/VIL compatibility with driving source.
SN74HC138DR	CMOS technology, wider VCC range (2–6 V), higher noise immunity, but slower at 5 V (21 ns typical), different input thresholds.	Preferred for mixed-voltage or battery-powered systems; incompatible with TTL-level inputs without conditioning.	Choose SN74HC138DR for modern low-power designs with 3.3 V or variable supply; avoid in legacy 5 V TTL-only systems without level translation.

Compared with SN74F138DR, SN74LS138N trades speed for lower static power, while SN74HC138DR offers supply flexibility and noise robustness at the cost of propagation latency and interface compatibility - making SN74F138DR optimal for legacy 5 V high-speed decoding where TTL interoperability is mandatory.

Availability

SN74F138DR is available at Aetrix Electronics and suitable for memory address decoding, peripheral selection, data routing, and logic signal multiplexing requiring stable component supply across industrial and embedded production programs.

Supply support for SN74F138DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial, automotive, and communications reach.

The SN74F138DR belongs to TI's 74F (Fast TTL) logic family, engineered for high-speed digital systems where minimal propagation delay and TTL compatibility are critical - particularly in memory subsystems and real-time control interfaces.

FAQ

What is the maximum operating frequency supported by SN74F138DR?

The SN74F138DR is not characterized for a maximum clock frequency because it is a combinational logic device without an internal clock. Its usable switching rate depends on input transition times and load capacitance. With CL = 50 pF and RL = 500 Ω, the worst-case propagation delay is 12.5 ns (tPHL from G1), supporting effective data routing or decoding up to approximately 40 MHz in tightly controlled systems. Always validate timing margins against your specific board layout and loading conditions when using SN74F138DR.

Can SN74F138DR drive LEDs directly?

Yes, SN74F138DR can drive LEDs directly via its active-low open-collector outputs (Y0–Y7). Each output sinks up to 20 mA at VOL ≤ 0.5 V, sufficient for standard indicator LEDs with appropriate series resistors (e.g., 220 Ω for 5 V supply and 15 mA LED current). Ensure total device ICC remains within 20 mA limit under simultaneous output loading, and confirm that VCC decoupling is adequate to prevent ground bounce. This capability is routinely used in SN74F138DR-based status panel designs.

Does SN74F138DR support cascading to decode more than 8 lines?

Yes, SN74F138DR supports cascading to implement larger decoders: two devices can create a 4-to-16 decoder using one device's outputs to enable the second, and three devices can build a 5-to-32 decoder. The dual active-low enables (G2A, G2B) and single active-high enable (G1) minimize external logic - a 24-line decoder requires zero inverters, and a 32-line version needs only one. This hierarchical expansion is explicitly documented in the SN74F138DR datasheet function tables and logic diagrams.

Is SN74F138DR pin-compatible with SN74LS138?

Yes, SN74F138DR is pin-compatible and functionally equivalent to SN74LS138 in the same SOIC-16 (D) or PDIP-16 (N) packages. Both share identical pin assignments, truth tables, and enable/input/output logic. However, SN74F138DR delivers significantly faster propagation (2.7–9 ns vs. 15–25 ns) and higher output drive (20 mA vs. 8 mA), making it a performance upgrade where timing is critical. No PCB changes are required when substituting SN74F138DR for SN74LS138 in existing designs.

What is the meaning of "DR" in SN74F138DR?

The "DR" suffix in SN74F138DR denotes Texas Instruments' packaging and packaging format: "D" indicates SOIC (Small Outline Integrated Circuit) package, and "R" specifies tape-and-reel delivery (2500 units per reel). This distinguishes it from SN74F138N (PDIP tube), SN74F138NSR (SOP tape-and-reel), and obsolete variants like SN74F138D (same SOIC package but non-RoHS, now obsolete). The SN74F138DR is RoHS-compliant, NIPDAU-finished, and MSL Level-1, confirming its suitability for automated SMT assembly processes.

SN74F138DR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74F

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: Decoder/Demultiplexer

Circuit:: 1 x 3:8

Independent Circuits:: 1

Current - Output High, Low:: 1mA, 20mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: 0°C ~ 70°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74F138DR FAQ

1.How can I place an order for SN74F138DR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74F138DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74F138DR reliable?

The price and inventory of SN74F138DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74F138DR is usually 5 days.

3.What payment methods are accepted for SN74F138DR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74F138DR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74F138DR?

SN74F138DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74F138DR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74F138DR?

For technical support, including SN74F138DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74F138DR requirements.

6.How does Aetrix verify that SN74F138DR is sourced from the original manufacturer or authorized distributors?

All SN74F138DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74F138DR meets industry standards.

7.What is the process for return or replacement of SN74F138DR?

All SN74F138DR units undergo pre-shipment inspection (PSI). If there is an issue with SN74F138DR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74F138DR part is unused and in its original packaging.

Return procedure for SN74F138DR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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