Texas Instruments SN74F138NS
- Part No.:
- SN74F138NS
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SN74F138NS.pdf
- Description:
- IC DECODER/DEMUX 1 X 3:8 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:740
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74F138NS from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC designed for high-speed memory decoding and data routing. It features three enable inputs (G1, G2A, G2B), active-low outputs, propagation delays as low as 2.7 ns (tPLH), operates at 4.5–5.5 V, and is rated for 0°C to 70°C industrial temperature range.
For engineers reviewing the SN74F138NS datasheet, SN74F138NS pinout, SN74F138NS application, or SN74F138NS equivalent, key selection considerations include its TTL-compatible input thresholds (VIL = 0.8 V, VIH = 2 V), 20 mA output sink capability, cascading support via dual active-low enables, and SOP-16 package compatibility with automated SMT assembly.
Technical Context
The SN74F138NS implements positive-logic binary decoding with three select inputs (A, B, C) and three independent enables (G1 high-active, G2A/G2B low-active), allowing flexible hierarchical expansion without external inverters. Its internal NAND-based architecture ensures deterministic output states per the function table.
It supports demultiplexing by using an enable input (e.g., G1) as a data line while A/B/C control channel selection - enabling 1-to-8 signal distribution. All outputs are active-low open-collector equivalents, compatible with standard TTL fanout and wired-OR bus configurations.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures stable operation across standard 5 V TTL rails with ±10% tolerance. |
| Propagation Delay | 2.7 ns (min tPLH, A→Y) - enables use in sub-100 MHz address decode paths without adding system timing margin. |
| Output Sink Current | 20 mA (IOL) - drives standard TTL loads directly; supports up to 10 LSTTL unit loads. |
| Input Thresholds | VIL = 0.8 V, VIH = 2.0 V - guarantees noise immunity and interoperability with legacy 5 V logic families. |
| Operating Temperature | 0°C to 70°C - qualified for commercial/industrial embedded systems, not extended or military grade. |
| Package Type | SOP-16 (NS) - surface-mount, 1.27 mm pitch, 10.4 mm × 5.3 mm footprint; RoHS-compliant, NIPDAU lead finish. |
Pinout & Package
SOP-16 (NS) package: 16-pin small-outline plastic package with gull-wing leads, 1.27 mm pitch, 10.4 mm × 5.3 mm body size, maximum height 2.00 mm, RoHS-compliant NIPDAU finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Enable Input | Active-low enable; must be low with G2B low and G1 high for decoding to occur. |
| 2 (G2B) | Enable Input | Second active-low enable; both G2A and G2B must be asserted for device activation. |
| 3 (G1) | Enable Input | Active-high enable; used as data input in demux mode when A/B/C set channel address. |
| 4 (C) | Select Input | MSB of 3-bit binary address; determines output Y0–Y7 mapping per function table. |
| 5 (B) | Select Input | Intermediate bit of address; combined with A and C to uniquely select one of eight outputs. |
| 6 (A) | Select Input | LSB of address; full 3-bit combination selects active-low output line Y0–Y7. |
| 7 (Y0) | Output | Active-low decoded output; low only when G1=H, G2A=L, G2B=L, and CBA=000. |
| 8 (GND) | Power | Ground reference for all internal circuitry and I/O; requires low-impedance PCB connection. |
| 9 (Y1) | Output | Active-low output for CBA=001; shares same electrical specs (VOH/VOL, IOL) as Y0–Y7. |
| 10 (Y2) | Output | Active-low output for CBA=010; electrically identical to other Yx outputs. |
| 11 (Y3) | Output | Active-low output for CBA=011; supports wired-OR bus interfacing due to open-collector behavior. |
| 12 (Y4) | Output | Active-low output for CBA=100; no internal pull-up; external pull-up required for logic HIGH level. |
| 13 (Y5) | Output | Active-low output for CBA=101; compatible with standard 5 V TTL and CMOS load conditions. |
| 14 (Y6) | Output | Active-low output for CBA=110; timing matches Y0–Y7 within ±0.5 ns across temperature. |
| 15 (Y7) | Output | Active-low output for CBA=111; final channel in 3-to-8 decode map; same drive strength as others. |
| 16 (VCC) | Power | +5 V supply rail; bypass capacitor (0.1 µF ceramic) recommended adjacent to pin for noise suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Three Enable Inputs | Enables seamless 24-line decoding without external inverters and 32-line with only one inverter - reduces board area and component count. |
| High-Speed Propagation | Typical tPLH/tPHL ≤ 5.7 ns at VCC = 5 V - minimizes added delay in memory access paths, preserving system timing budgets. |
| TTL-Compatible Interface | VIH = 2.0 V / VIL = 0.8 V and IOL = 20 mA - ensures direct interconnection with legacy 74-series and microcontroller GPIOs without level-shifting. |
| Demultiplexer Mode | G1 functions as data input while A/B/C act as channel selectors - provides 1-to-8 signal distribution without additional logic gates. |
| SOP-16 Packaging | RoHS-compliant, tape-and-reel (2000 pcs/reel), MSL Level-1 - supports high-volume automated assembly and long-term supply stability. |
Applications
| Memory Address Decoding | Peripheral Select Logic |
|---|---|
Use Scenario: Decoding 3-bit address lines in an 8-KB SRAM subsystem to activate individual memory blocks or chip-select signals. IC Role / Device Role / Timing Role: Primary address decoder that translates CPU address bits into discrete chip-enable signals for parallel memory banks. Use Value: Propagation delay under 8 ns ensures decoder latency does not extend effective memory access time beyond SRAM tAA specification. | Use Scenario: Selecting among eight UART, SPI, or GPIO expanders connected to a microcontroller's shared data bus. IC Role / Device Role / Timing Role: Bus-controlled peripheral selector that asserts one active-low CS line per addressed device. Use Value: Three enable inputs allow synchronization with microcontroller control signals (e.g., RD/WR strobes), preventing spurious selections during bus transitions. |
| LED Segment Driver Control | Data Routing in Test Equipment |
Use Scenario: Driving common-cathode 7-segment LED displays where each segment corresponds to one Yx output. IC Role / Device Role / Timing Role: Static segment enable controller translating 3-bit digit position code into individual segment activation. Use Value: 20 mA sink capability directly drives standard LEDs without external transistors, simplifying BOM and layout. | Use Scenario: Routing test signals from a single ATE source to one of eight DUT channels in automated functional testing. IC Role / Device Role / Timing Role: Signal path selector operating in demux mode with G1 as data input and A/B/C as channel address. Use Value: Active-low outputs interface cleanly with TTL-level test fixtures; low propagation delay maintains signal integrity at 50 MHz switching rates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS138N | Slower propagation (15–20 ns), lower ICC (2 mA), same pinout and logic function. | Better suited for low-power, non-critical timing applications; not appropriate for high-speed memory systems. | Choose SN74LS138N only if speed is not constrained and power budget is tighter than 13 mA typical ICC. |
| SN74HC138DR | CMOS technology, wider VCC range (2–6 V), higher noise immunity, but 5 V-only compatible with SN74F138NS in mixed-signal designs. | Requires level translation when interfacing with legacy 5 V TTL buses; unsuitable for direct replacement without validation. | Prefer SN74HC138DR only in new designs targeting 3.3 V or battery-powered systems; verify VIH/VIL margins before substitution. |
Compared with SN74LS138N and SN74HC138DR, the SN74F138NS delivers optimal balance of speed, TTL compatibility, and industrial temperature range - making it the preferred choice for legacy 5 V embedded systems requiring sub-10 ns decode latency.
Availability
SN74F138NS is available at Aetrix Electronics and suitable for memory decoding, peripheral selection, LED driver control, and automated test equipment requiring stable component supply and long-term industrial-grade availability.
Supply support for SN74F138NS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial and automotive qualification.
The SN74F138NS belongs to TI's 74F family of fast TTL logic devices, engineered specifically for high-speed memory decoding and data-routing applications where propagation delay and fanout are critical design parameters.
FAQ
What is the maximum clock or signal frequency supported by the SN74F138NS?
The SN74F138NS is not a clocked device and has no specified maximum operating frequency. Its performance is defined by propagation delay (2.7–9 ns), making it suitable for address decode and static selection tasks in systems with memory access times ≥15 ns. For dynamic routing, ensure setup/hold timing relative to enable and select edges is met per the function table.
Does the SN74F138NS require external pull-up resistors on its outputs?
Yes, the SN74F138NS outputs are active-low and internally open-collector equivalents. External pull-up resistors (typically 1–10 kΩ to VCC) are required to establish a valid HIGH logic level on Y0–Y7. The value depends on capacitive load and desired rise time; 4.7 kΩ is commonly used for TTL-compatible bus driving.
Can the SN74F138NS be used as a 1-to-8 demultiplexer?
Yes, the SN74F138NS can operate as a demultiplexer by using G1 as the data input and A/B/C as the 3-bit channel address. When G2A and G2B are held low and G1 toggles, the selected Yx output mirrors G1's state (inverted due to active-low output). This configuration requires no additional logic and is explicitly supported in the datasheet.
Is the SN74F138NS pin-compatible with the SN74LS138N?
Yes, the SN74F138NS and SN74LS138N share identical pinouts, logic function, and DC electrical specifications (VIL/VIH, VOL/VOH). However, SN74F138NS offers significantly faster propagation (≤9 ns vs. ≤20 ns) and higher ICC (13–20 mA vs. ~2 mA), so thermal and power delivery must be re-evaluated in drop-in replacements.
What is the meaning of "NS" in SN74F138NS?
The "NS" suffix in SN74F138NS denotes the SOP (Small Outline Package) variant with 16 pins, standardized under TI's NS0016A package drawing. It indicates a surface-mount, gull-wing leaded plastic package with 1.27 mm pitch, distinct from PDIP (N), SOIC (D), or ceramic packages - critical for PCB land pattern and assembly process selection.
SN74F138NS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74F
- Package/Case:
- 16-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 1mA, 20mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
SN74F138NS FAQ
1.How can I place an order for SN74F138NS through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74F138NS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74F138NS reliable?
The price and inventory of SN74F138NS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74F138NS is usually 5 days.
3.What payment methods are accepted for SN74F138NS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74F138NS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74F138NS?
SN74F138NS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74F138NS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74F138NS?
For technical support, including SN74F138NS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74F138NS requirements.
6.How does Aetrix verify that SN74F138NS is sourced from the original manufacturer or authorized distributors?
All SN74F138NS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74F138NS meets industry standards.
7.What is the process for return or replacement of SN74F138NS?
All SN74F138NS units undergo pre-shipment inspection (PSI). If there is an issue with SN74F138NS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74F138NS part is unused and in its original packaging.
Return procedure for SN74F138NS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74F138NS Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
