Texas Instruments SN74F157ADR
- Part No.:
- SN74F157ADR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74F157ADR.pdf
- Description:
- IC MULTIPLEXER 4 X 2:1 16SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74F157ADR from Texas Instruments is a quad 2-input data selector/multiplexer with common strobe (G) control, operating at 4.5–5.5 V supply, delivering true logic outputs, 6.5 ns max tPHL (A/B→Y), and 11 ns max tPLH (G→Y) at 5 V/25°C. It routes one of two 4-bit input sources to four outputs in TTL-compatible digital systems such as address/data bus switching in legacy microprocessor peripherals.
For engineers reviewing the SN74F157ADR datasheet, SN74F157ADR pinout, SN74F157ADR application, or SN74F157ADR equivalent, key selection criteria include strobe-controlled 4-bit multiplexing capability, SOIC-16 package compatibility, guaranteed 0°C to 70°C operation, TTL-level input thresholds (VIL ≤ 0.8 V, VIH ≥ 2 V), and output drive strength (IOL = 20 mA, IOH = −1 mA).
Technical Context
The SN74F157ADR implements four independent 2:1 multiplexers sharing a single active-low enable (G) input and a common select line (A/B). When G is high, all Y outputs are forced low regardless of A/B or data inputs; when G is low, the A/B signal selects whether inputs A1–A4 or B1–B4 appear at outputs Y1–Y4.
It uses standard bipolar TTL circuitry with buffered inputs and outputs, supporting fan-out of 10 LS-TTL loads. Its propagation delays are asymmetric: tPHL (A/B→Y) is faster (≤7 ns) than tPLH (≤11 ns), reflecting inherent transistor turn-on/off timing differences in the F-series process.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 4.5 V to 5.5 V - Ensures stable operation within standard TTL power rail tolerances; not rated for 3.3 V or wide-voltage use. |
| Operating Temperature | 0°C to 70°C - Commercial-grade rating; excludes extended or industrial temperature range support. |
| Propagation Delay (tPHL) | ≤7 ns (A/B → Y) - Enables reliable 100+ MHz clock-domain handshaking in synchronous bus arbitration. |
| Output Drive (IOL) | 20 mA (low-state) - Sufficient to directly drive multiple LS-TTL inputs or small LED indicators without buffering. |
| Input Thresholds | VIL ≤ 0.8 V, VIH ≥ 2.0 V - Matches standard TTL logic families; incompatible with CMOS-level signaling without level translation. |
| Quiescent Current (ICC) | 15.5–23 mA - Reflects typical bipolar TTL static power consumption; higher than modern low-power logic. |
Pinout & Package
SN74F157ADR is supplied in a 16-pin SOIC (D) package per TI's packaging addendum, with 7.5 mm body width, 1.75 mm height max, and 1.27 mm lead pitch. Pin 1 is located in quadrant Q1 per tape-and-reel orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (1A) | Data Input A, Channel 1 | First bit of source-A 4-bit word; routed to Y1 when A/B = L and G = L. |
| 2 (1B) | Data Input B, Channel 1 | First bit of source-B 4-bit word; routed to Y1 when A/B = H and G = L. |
| 3 (1Y) | Output, Channel 1 | Active-high true output; reflects selected A1 or B1; low when G = H. |
| 4 (2A) | Data Input A, Channel 2 | Second bit of source-A word; paired with 2B and 2Y for parallel 4-bit selection. |
| 5 (2B) | Data Input B, Channel 2 | Second bit of source-B word; synchronized selection with other channels via shared A/B and G. |
| 6 (2Y) | Output, Channel 2 | True output for channel 2; no inversion; same enable behavior as 1Y, 3Y, 4Y. |
| 7 (3A) | Data Input A, Channel 3 | Third bit of source-A; occupies pin 7 in D-package top view; matches functional grouping. |
| 8 (3B) | Data Input B, Channel 3 | Third bit of source-B; complements 3A under A/B control; shares strobe with all channels. |
| 9 (3Y) | Output, Channel 3 | Third selected output; driven only when G = L; zero-latency correlation with A/B state. |
| 10 (4A) | Data Input A, Channel 4 | Fourth and final bit of source-A; completes 4-bit word routing capability. |
| 11 (4B) | Data Input B, Channel 4 | Fourth bit of source-B; enables full byte-wide multiplexing between two data sources. |
| 12 (4Y) | Output, Channel 4 | Final output of quad mux; identical timing and drive specs as other Y outputs. |
| 13 (A/B) | Common Select Line | Single control determining source: L → route A1–A4; H → route B1–B4 to respective Y outputs. |
| 14 (G) | Common Strobe / Enable | Active-low global enable: H forces all Y outputs low; L enables normal multiplexing function. |
| 15 (VCC) | Positive Supply | Connects to +5 V rail; decoupling capacitor recommended near pin for noise suppression. |
| 16 (GND) | Ground Reference | System ground return; must be low-impedance path to minimize switching noise coupling. |
Key Features
| Feature | Design Value |
|---|---|
| Quad 2:1 Multiplexing | Four independent channels share one A/B select and one G strobe-reduces control logic overhead in bus-switching applications. |
| True Output Logic | Outputs replicate selected inputs without inversion-eliminates need for external inverters in data path integrity-critical designs. |
| TTL-Compatible Interface | Meets standard TTL voltage thresholds and drive strength-ensures interoperability with 74LS, 74S, and legacy microcontroller peripherals. |
| Strobe-Controlled Output Disable | G input forces all outputs low when high-provides clean bus isolation during arbitration or standby without external gating. |
| SOIC-16 Packaging | Surface-mount D package (7.5 mm × 10.3 mm) supports automated assembly and offers better thermal performance than PDIP alternatives. |
Applications
| Microprocessor Address Bus Switching | Legacy Memory Bank Selection |
|---|---|
|
Use Scenario: Selecting between two memory-mapped peripheral address ranges in an 8-bit CPU system (e.g., Z80 or 8085). IC Role / Device Role / Timing Role: Quad 2:1 mux routes upper address bits (A8–A11) based on decoded bank signal and global strobe. Use Value: Enables dual-ROM or ROM/RAM bank switching with single-cycle latency and no added glue logic beyond decode gates. |
Use Scenario: Isolating alternate firmware images or configuration tables stored in separate EPROM banks. IC Role / Device Role / Timing Role: Acts as address-path selector controlled by boot-mode jumper or status register bit. Use Value: Allows field-upgradable firmware without hardware modification; strobe (G) synchronizes switch to clock edge. |
| Parallel Data Path Routing | Digital Test Equipment Signal Gating |
|
Use Scenario: Directing test pattern data from two pattern generators to a single DUT interface connector. IC Role / Device Role / Timing Role: Routes 4-bit nibble streams under microcontroller command; G ensures glitch-free transitions. Use Value: Reduces PCB trace count vs. discrete gate solutions; maintains signal integrity with matched propagation paths. |
Use Scenario: Enabling/disabling stimulus signals to DUT pins during boundary-scan or functional test sequences. IC Role / Device Role / Timing Role: Functions as programmable signal gate where A/B selects test vector source and G enables output. Use Value: Provides deterministic signal blanking during test state changes-prevents metastability or false triggering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 2:1 multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS157N | Lower ICC (19 mA typ), slower tPLH (25 ns max), same pinout and logic function. | Better suited for low-power, non-speed-critical legacy systems; not drop-in for F-series timing margins. | Select when power efficiency outweighs speed; verify setup/hold timing with downstream logic. |
| SN74HC157DR | CMOS technology, 2–6 V supply, VIH/VIL compatible with both TTL and CMOS, 23 ns max tPD at 4.5 V. | Enables mixed-voltage designs and reduces static power; requires level-shifting if interfacing with pure TTL. | Choose for new designs needing wider VCC range or lower quiescent current; validate noise immunity in noisy environments. |
Compared with SN74F157ADR, SN74LS157N trades speed for reduced power, while SN74HC157DR shifts to CMOS operation with broader supply flexibility but different noise margin and loading behavior-neither is pin-compatible without timing or interface validation.
Availability
SN74F157ADR is available at Aetrix Electronics and suitable for microprocessor bus switching, legacy memory expansion, parallel data routing, and digital test equipment requiring stable component supply across long-lifecycle industrial deployments.
Supply support for SN74F157ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.
The SN74F157ADR belongs to TI's 74F fast TTL logic family, designed for high-speed digital control in computing, instrumentation, and communications equipment where propagation delay and fan-out were critical constraints.
FAQ
What is the maximum clock frequency supported by SN74F157ADR?
The SN74F157ADR does not operate on a clock signal-it is combinatorial logic with propagation delays specified up to 11 ns (tPLH, G→Y). In practice, it supports data rates up to ~90 MHz for clean, well-terminated 4-bit bus switching when used with appropriate setup/hold margins relative to controlling logic.
Is SN74F157ADR compatible with 3.3 V logic systems?
No, SN74F157ADR is not 3.3 V compatible. Its absolute maximum VCC is 7 V, but recommended operation is strictly 4.5–5.5 V. Input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and output levels (VOH ≥ 2.5 V at IOH = −1 mA) assume a 5 V supply; interfacing with 3.3 V systems requires level translation.
Does SN74F157ADR have internal pull-up or pull-down resistors on its inputs?
No, SN74F157ADR has no internal pull-up or pull-down resistors. All inputs-A/B, G, and data lines-must be actively driven to valid TTL logic levels; floating inputs may cause unpredictable output states or increased power consumption due to input stage bias instability.
Can SN74F157ADR drive LEDs directly?
Yes, SN74F157ADR can drive LEDs directly in active-low configuration: connect LED anode to VCC and cathode to Y output through a current-limiting resistor. With IOL = 20 mA, it supports up to ~15 mA LED current (using 220 Ω at 5 V), sufficient for indicator use but not high-brightness arrays.
What is the meaning of "F157A" marking on SN74F157ADR devices?
The "F157A" marking on SN74F157ADR refers to the functional identifier per TI's standard part numbering: "F" denotes the 74F fast TTL family, "157" is the base device number for quad 2-input multiplexers, and "A" indicates the improved version with tighter AC/DC specifications versus original '157 design-this marking appears on the top surface of the SOIC package.
SN74F157ADR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74F
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Multiplexer
- Circuit:
- 4 x 2:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 1mA, 20mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74F157ADR FAQ
1.How can I place an order for SN74F157ADR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74F157ADR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74F157ADR reliable?
The price and inventory of SN74F157ADR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74F157ADR is usually 5 days.
3.What payment methods are accepted for SN74F157ADR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74F157ADR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74F157ADR?
SN74F157ADR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74F157ADR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74F157ADR?
For technical support, including SN74F157ADR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74F157ADR requirements.
6.How does Aetrix verify that SN74F157ADR is sourced from the original manufacturer or authorized distributors?
All SN74F157ADR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74F157ADR meets industry standards.
7.What is the process for return or replacement of SN74F157ADR?
All SN74F157ADR units undergo pre-shipment inspection (PSI). If there is an issue with SN74F157ADR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74F157ADR part is unused and in its original packaging.
Return procedure for SN74F157ADR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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