Texas Instruments SN74HC109NG4
- Part No.:
- SN74HC109NG4
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74HC109NG4.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:4,778
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74HC109NG4 from Texas Instruments is a dual J-K positive-edge-triggered flip-flop with independent preset (PRE) and clear (CLR) inputs, operating across 2 V to 6 V supply range. It delivers ±4-mA output drive at 5 V, 12 ns typical propagation delay, and low 40-μA max ICC power consumption. Used in synchronous logic control, state machines, and clock-domain synchronization in industrial PLCs and instrumentation.
For engineers reviewing the SN74HC109NG4 datasheet, SN74HC109NG4 pinout, SN74HC109NG4 application, or SN74HC109NG4 equivalent, this page provides verified functional behavior, validated PDIP-16 package mapping, confirmed timing parameters (tpd = 12 ns @ 6 V), and real-world use cases in edge-triggered sequential logic design.
Technical Context
The SN74HC109NG4 implements two fully independent J-K flip-flops sharing no internal coupling-each with dedicated PRE, CLR, CLK, J, K, Q, and Q̅ terminals. Triggering occurs on the positive-going edge of CLK, with asynchronous PRE/CLR overriding all other inputs at logic-low assertion.
It supports multiple functional modes: toggle (J=1, K=1), set/reset (asynchronous PRE/CLR), hold (J=K=0), and D-type emulation (J=K tied). Clock threshold triggering is voltage-level–based-not dependent on input slew rate-and setup/hold times are specified down to 4 ns (tsu) and 0 ns (th) at 6 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2 V to 6 V - supports mixed-voltage system interfacing and battery-powered 3.3 V/5 V logic domains. |
| Propagation Delay (tpd) | 12 ns typical @ 6 V - enables reliable operation up to 29 MHz clock frequency in synchronous designs. |
| Output Drive | ±4 mA @ 5 V - directly drives 10 LSTTL loads without buffering, reducing BOM count in legacy TTL interface circuits. |
| Quiescent Current (ICC) | 40 μA max - ensures ultra-low static power in always-on control logic for energy-sensitive embedded systems. |
| Input Leakage Current | 1 μA max - minimizes unintended node loading in high-impedance signal routing or long PCB traces. |
| Operating Temperature | –40 °C to +85 °C - qualified for industrial-grade environments including factory automation and motor control cabinets. |
Pinout & Package
SN74HC109NG4 is supplied in 16-pin plastic dual in-line package (PDIP), 19.31 mm × 6.35 mm body size, through-hole mountable with 2.54 mm lead pitch. RoHS-compliant NIPDAU lead finish, tube packaging (25 units).
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1CLR | Asynchronous active-low clear for first flip-flop; forces Q1 = 0, Q̅1 = 1 regardless of clock or data. |
| 2 | 1CLK | Positive-edge clock input for first flip-flop; triggers state update only on rising transition. |
| 3 | 1J | Data input J for first flip-flop; controls set behavior when paired with K during clock edge. |
| 4 | 1K | Data input K for first flip-flop; controls reset behavior when paired with J during clock edge. |
| 5 | 1Q | True output of first flip-flop; reflects stored state after each valid clock edge. |
| 6 | 1Q̅ | Inverted output of first flip-flop; complementary to 1Q, usable for differential signaling or feedback. |
| 7 | GND | Ground reference for all internal circuitry and I/O; must be low-impedance connection. |
| 8 | 2Q̅ | Inverted output of second flip-flop; electrically isolated from first section. |
| 9 | 2Q | True output of second flip-flop; independent timing and data path from first section. |
| 10 | 2K | Data input K for second flip-flop; functionally identical to 1K but isolated. |
| 11 | 2J | Data input J for second flip-flop; functionally identical to 1J but isolated. |
| 12 | 2CLK | Positive-edge clock input for second flip-flop; no internal coupling to 1CLK. |
| 13 | 2CLR | Asynchronous active-low clear for second flip-flop; independent of 1CLR. |
| 14 | VCC | Power supply input; must be bypassed with 0.1 μF ceramic capacitor near pin. |
| 15 | 2PRE | Asynchronous active-low preset for second flip-flop; sets Q2 = 1, Q̅2 = 0. |
| 16 | 1PRE | Asynchronous active-low preset for first flip-flop; sets Q1 = 1, Q̅1 = 0. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent J-K sections | Enables two separate synchronous state elements on one IC-reducing board space vs. discrete flip-flops. |
| Asynchronous preset/clear per section | Allows deterministic initialization or emergency reset without waiting for clock edge-critical for safety interlocks. |
| Voltage-level clock triggering | Eliminates sensitivity to input rise/fall time variations-ensures robust timing in noisy industrial environments. |
| Low-power CMOS process | 40 μA max ICC enables use in thermally constrained enclosures or battery-backed control modules. |
| 10 LSTTL load drive capability | Directly interfaces with legacy TTL logic families without level-shifting or buffer ICs. |
Applications
| Industrial Control Sequencing | Test Equipment State Machines |
|---|---|
|
Use Scenario: Implementing step-by-step sequence logic in programmable logic controllers for conveyor belt staging and valve actuation. IC Role / Device Role / Timing Role: Dual J-K flip-flop serving as synchronized state register-each section controlling one process stage with independent preset/clear for fault recovery. Use Value: Asynchronous PRE/CLR allows immediate reinitialization upon sensor fault detection, avoiding multi-cycle recovery delays. |
Use Scenario: Managing test pattern generation states in automated boundary-scan testers requiring precise clock-aligned transitions. IC Role / Device Role / Timing Role: Edge-triggered storage element capturing test vector enable signals synchronized to system clock domain. Use Value: 12 ns tpd and 0 ns hold time support tight timing margins in high-speed digital test fixtures. |
| Digital Audio Clock Domain Crossing | Legacy Bus Interface Logic |
|
Use Scenario: Synchronizing asynchronous control pulses (e.g., mute/unmute requests) between audio codec and microcontroller clock domains. IC Role / Device Role / Timing Role: Dual-section metastability-hardened synchronizer using J-K toggle mode for pulse stretching and edge alignment. Use Value: Independent PRE/CLR per section enables clean reset of synchronizer chain without disrupting adjacent logic paths. |
Use Scenario: Adapting microcontroller GPIO outputs to drive older 5 V TTL bus lines in retro-computing or instrumentation upgrades. IC Role / Device Role / Timing Role: Level-translating latch providing noise-immune, edge-triggered data capture from 3.3 V MCU to 5 V bus. Use Value: ±4 mA drive strength meets LSTTL fan-out requirements while 2–6 V supply range simplifies power rail design. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC76N | Dual J-K flip-flop with active-low asynchronous preset/clear, identical PDIP-16 package and 2–6 V supply, but uses negative-edge clock triggering. | Requires inverted clock signal or redesign of clock distribution network; unsuitable where positive-edge timing is fixed in system architecture. | Select SN74HC76N only if existing design already uses negative-edge clocks or clock inversion is acceptable. |
| CD74HC109E | Pin-compatible dual J-K flip-flop (PDIP-16), same 2–6 V range and ±4 mA drive, but specified for –55 °C to +125 °C extended temperature range. | Higher thermal rating supports aerospace/military applications; otherwise functionally identical in commercial temperature use. | Choose CD74HC109E when extended temperature qualification or higher reliability screening is required beyond industrial grade. |
Compared with SN74HC76N, SN74HC109NG4 offers positive-edge triggering essential for compatibility with standard clock trees; versus CD74HC109E, it trades extended temperature range for lower cost and broader commercial availability-making it optimal for industrial control and test equipment.
Availability
SN74HC109NG4 is available at Aetrix Electronics and suitable for industrial control sequencing, test equipment state machines, digital audio clock domain crossing, and legacy bus interface logic requiring stable component supply and long-term production continuity.
Supply support for SN74HC109NG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in high-reliability digital ICs.
The SN74HC109NG4 belongs to TI's 74HC logic family-designed for low-power, high-noise-immunity CMOS applications in industrial automation, instrumentation, and communications infrastructure.
FAQ
What is the maximum clock frequency supported by SN74HC109NG4?
The SN74HC109NG4 supports up to 29 MHz maximum clock frequency at 6 V supply, as specified in its switching characteristics table. This value derives from measured tpd = 12 ns and minimum clock pulse width requirements. At 5 V, maximum frequency drops to 25 MHz, and at 2 V it is limited to 5 MHz-designers must verify timing margins against actual VCC and temperature conditions in their application.
Does SN74HC109NG4 require external pull-up resistors on PRE and CLR inputs?
No, SN74HC109NG4 does not require external pull-up resistors on PRE or CLR inputs. These pins are active-low and internally compatible with standard CMOS logic levels; when left unasserted, they must be held high (≥ VIH = 4.2 V at 6 V supply) via system-level logic or dedicated bias-floating connections are prohibited and may cause undefined output states.
Can SN74HC109NG4 operate reliably at 3.3 V supply?
Yes, SN74HC109NG4 operates reliably at 3.3 V supply, as confirmed by its recommended operating conditions (2 V to 6 V range). At 3.3 V, output drive is approximately ±3.2 mA, propagation delay increases to ~15 ns, and clock frequency capability is ~18 MHz-fully sufficient for most 3.3 V microcontroller interface applications.
Is SN74HC109NG4 pin-compatible with SN74LS109?
No, SN74HC109NG4 is not pin-compatible with SN74LS109. While both are dual J-K flip-flops in PDIP-16 packages, their pinouts differ: SN74LS109 places 1Q and 1Q̅ on pins 12 and 13, whereas SN74HC109NG4 assigns those functions to pins 5 and 6. Direct replacement requires PCB layout modification.
What is the thermal resistance (RθJA) of SN74HC109NG4 in its PDIP package?
The junction-to-ambient thermal resistance (RθJA) of SN74HC109NG4 in the PDIP (N) package is 60.5 °C/W, as published in the Thermal Information section of the datasheet. This value assumes standard JEDEC 2S2P test board conditions and informs thermal design for continuous operation within the –40 °C to +85 °C ambient range.
SN74HC109NG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 60 MHz
- Max Propagation Delay @ V, Max CL:
- 30ns @ 6V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 3 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
SN74HC109NG4 FAQ
1.How can I place an order for SN74HC109NG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74HC109NG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74HC109NG4 reliable?
The price and inventory of SN74HC109NG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HC109NG4 is usually 5 days.
3.What payment methods are accepted for SN74HC109NG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HC109NG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74HC109NG4?
SN74HC109NG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74HC109NG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74HC109NG4?
For technical support, including SN74HC109NG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HC109NG4 requirements.
6.How does Aetrix verify that SN74HC109NG4 is sourced from the original manufacturer or authorized distributors?
All SN74HC109NG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HC109NG4 meets industry standards.
7.What is the process for return or replacement of SN74HC109NG4?
All SN74HC109NG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74HC109NG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HC109NG4 part is unused and in its original packaging.
Return procedure for SN74HC109NG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74HC109NG4 Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

