Texas Instruments SN74HC112D
- Part No.:
- SN74HC112D
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74HC112D.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:1,279
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Product details
Overview
SN74HC112D from Texas Instruments is a dual J-K negative-edge-triggered flip-flop IC with independent preset (PRE) and clear (CLR) inputs, 2V–6V supply range, typical propagation delay of 13ns at 6V, ±4mA output drive at 5V, and low ICC of 40μA max - used in synchronous logic control for LED display row/column drivers and network switch state management.
For engineers reviewing the SN74HC112D datasheet, SN74HC112D pinout, SN74HC112D application, or SN74HC112D equivalent, key selection criteria include negative-edge clock triggering behavior, asynchronous PRE/CLR priority over clocked J/K data, SOIC-16 package thermal resistance (RθJA = 117.2°C/W), and compatibility with LSTTL load interfacing.
Technical Context
The SN74HC112D implements two fully independent J-K flip-flops sharing no internal coupling; each features asynchronous active-low PRE and CLR that override clocked operation. Clock triggering occurs at a defined voltage threshold on the falling edge-not dependent on CLK fall time-enabling robust timing in noisy environments.
Each flip-flop supports toggle mode when J=K=HIGH, retains state during HOLD (th = 0ns), and accepts setup times as low as 17ns at 6V. Input clamp current is ±20mA, and outputs meet standard CMOS VOH/VOL specs across 2V–6V VCC with guaranteed 4mA sink/source at 5V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | High-speed CMOS (74HC), compatible with TTL input thresholds and driving 10 LSTTL loads |
| Supply Voltage Range | 2V to 6V - enables direct interface with 3.3V and 5V systems without level shifting |
| Propagation Delay (tpd) | 13ns typical at 6V - determines maximum clock frequency (24MHz max at 6V) |
| Output Drive | ±4mA at 5V - sufficient to directly drive LEDs or small logic loads without buffers |
| Quiescent Current (ICC) | 40μA max - supports low-power standby modes in battery-backed or energy-sensitive designs |
| Input Leakage (II) | ±1μA max - prevents unintended state changes from floating inputs in high-impedance configurations |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade embedded control applications |
Pinout & Package
SN74HC112D uses a 16-pin SOIC (Small Outline Integrated Circuit) package measuring 9.9mm × 6.0mm (body) with 1.27mm pitch; suitable for automated SMT assembly and offers moderate thermal performance (RθJA = 117.2°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 10, 11, 12, 13, 14, 15 | J, K, CLK, PRE, CLR, Q, Q̅ (per flip-flop) | Dual independent channels: Pins 1–7 (U1) and 8–15 (U2) - each with full J/K/CLK/PRE/CLR/Q/Q̅ set |
| 7 | GND | Power return reference for both flip-flops; must be low-impedance for noise immunity |
| 16 | VCC | Positive supply rail; requires local 0.1μF bypass capacitor per device to suppress switching transients |
Key Features
| Feature | Design Value |
|---|---|
| Negative-edge clock triggering | Ensures deterministic sampling on falling CLK edge - eliminates race conditions in cascaded counters |
| Asynchronous preset/clear | Immediate Q/Q̅ forcing to HIGH/LOW regardless of CLK or J/K state - critical for power-up initialization |
| Wide VCC tolerance (2–6V) | Supports mixed-voltage system integration without external regulators or translators |
| Low input current (≤1μA) | Enables direct connection to high-impedance microcontroller GPIOs without loading effects |
| Toggle mode via J=K=HIGH | Reduces external logic count in divide-by-2 or oscillator circuits - simplifies clock division design |
Applications
| LED Display Control | Network Switch State Buffering |
|---|---|
Use Scenario: Driving multiplexed 7-segment or dot-matrix displays requiring precise row/column enable sequencing. IC Role / Device Role / Timing Role: Dual J-K flip-flop provides synchronized latch control for display scan lines and data hold registers. Use Value: Negative-edge triggering ensures clean transition between display frames; PRE/CLR allows instant blanking or reset during fault recovery. | Use Scenario: Storing port link status and configuration flags in Ethernet switch ASIC support circuitry. IC Role / Device Role / Timing Role: Edge-triggered storage element capturing PHY-ready signals and MAC handshake acknowledgments. Use Value: Asynchronous clear enables immediate port reset on link loss; 4mA drive supports direct interface with optocoupler inputs. |
| Motor Driver Sequencing | I/O Expansion for Microcontrollers |
Use Scenario: Generating complementary PWM phases for H-bridge gate drivers in stepper or BLDC motor controllers. IC Role / Device Role / Timing Role: Toggle-mode J-K flip-flop divides master clock to produce 50% duty-cycle complementary outputs. Use Value: Eliminates need for dedicated clock dividers; SOIC-16 footprint fits compact motor control PCB layouts. | Use Scenario: Extending GPIO count for industrial PLC modules using limited-pin microcontrollers. IC Role / Device Role / Timing Role: Synchronous register capturing parallel data from MCU and latching it for peripheral address/data bus control. Use Value: 2V–6V operation matches diverse MCU I/O voltages; low ICC reduces overall system standby power. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT112D | TTL-compatible input thresholds (VIH = 2V min), slightly higher ICC (80μA max), same pinout and function | Better suited for mixed 5V TTL/CMOS systems where input noise margin is critical | Choose when interfacing legacy 5V TTL logic without level shifters |
| 74AC112M | Faster tpd (9ns typ at 5V), higher drive (±24mA), wider temp range (−40°C to +125°C), same SOIC-16 package | Preferred for high-speed industrial automation where timing margins are tight | Choose when >20MHz operation or extended temperature range is required |
Compared with SN74HC112D, SN74HCT112D improves noise immunity in 5V TTL environments but increases static power, while 74AC112M delivers superior speed and drive strength at the cost of higher quiescent current - all retain identical pinout and functional behavior for drop-in evaluation.
Availability
SN74HC112D is available at Aetrix Electronics and suitable for LED display control, network switch buffering, and motor driver sequencing requiring stable component supply and long-term industrial availability.
Supply support for SN74HC112D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and logic solutions with emphasis on reliability, longevity, and broad industrial qualification.
The SN74HC112D belongs to TI's 74HC logic family - designed specifically for low-power, high-noise-immunity digital control in industrial, telecom, and computing infrastructure where predictable edge-triggered state retention is essential.
FAQ
What is the maximum clock frequency supported by the SN74HC112D?
The SN74HC112D supports up to 24MHz maximum clock frequency at VCC = 6V and TA = 25°C, as specified in the switching characteristics table. At 5V, the maximum is 20MHz, and at 2V it drops to 4MHz. These values assume proper load conditions (CL = 50pF) and valid input transition times - exceeding them may cause metastability or incorrect state capture in the SN74HC112D.
Does the SN74HC112D support asynchronous reset and set operations?
Yes, the SN74HC112D provides true asynchronous preset (PRE) and clear (CLR) inputs - both active-low - which force Q to HIGH or LOW respectively, independent of clock or J/K inputs. This behavior is guaranteed across the full operating voltage and temperature range, making the SN74HC112D suitable for reliable power-on initialization and fault recovery sequences.
Can the SN74HC112D operate at 3.3V supply voltage?
Yes, the SN74HC112D is fully specified for operation from 2V to 6V, including 3.3V. At 3.3V, it delivers typical propagation delay of ~15ns, output drive of ±3mA, and maintains VIH/VIL thresholds compatible with standard 3.3V logic families - confirming robust interoperability in mixed-voltage digital systems using the SN74HC112D.
What is the recommended bypass capacitor for the SN74HC112D?
Texas Instruments recommends a 0.1μF ceramic capacitor placed as close as possible to the VCC (pin 16) and GND (pin 7) pins of the SN74HC112D to suppress high-frequency switching noise. For enhanced stability in noisy environments, a parallel 1μF capacitor may be added - but the 0.1μF unit is mandatory for reliable operation of the SN74HC112D under dynamic load conditions.
Is the SN74HC112D pin-compatible with older 74LS112 devices?
No, the SN74HC112D is not pin-compatible with the bipolar 74LS112 - although both are dual J-K flip-flops in 16-pin packages, their pin assignments differ significantly (e.g., 74LS112 places VCC at pin 14 and GND at pin 7, while SN74HC112D uses pin 16 and pin 7). Direct replacement requires PCB layout revision; functional equivalence exists only at the logic level, not the physical interface of the SN74HC112D.
SN74HC112D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 60 MHz
- Max Propagation Delay @ V, Max CL:
- 21ns @ 6V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage - Supply:
- 2V ~ 6V
- Current - Quiescent (Iq):
- 4 µA
- Input Capacitance:
- 3 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74HC112D FAQ
1.How can I place an order for SN74HC112D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74HC112D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74HC112D reliable?
The price and inventory of SN74HC112D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HC112D is usually 5 days.
3.What payment methods are accepted for SN74HC112D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HC112D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74HC112D?
SN74HC112D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74HC112D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74HC112D?
For technical support, including SN74HC112D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HC112D requirements.
6.How does Aetrix verify that SN74HC112D is sourced from the original manufacturer or authorized distributors?
All SN74HC112D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HC112D meets industry standards.
7.What is the process for return or replacement of SN74HC112D?
All SN74HC112D units undergo pre-shipment inspection (PSI). If there is an issue with SN74HC112D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HC112D part is unused and in its original packaging.
Return procedure for SN74HC112D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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