Texas Instruments SN74HC138QDRG4Q1
- Part No.:
- SN74HC138QDRG4Q1
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74HC138QDRG4Q1.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:2,289
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74HC138QDRG4Q1 from Texas Instruments is an automotive-qualified 3-line-to-8-line decoder/demultiplexer in SOIC-16 package, operating from 2 V to 6 V, with typical propagation delay of 15 ns at 5 V, ±4-mA output drive, and low 80-µA max ICC - used for memory decoding and data routing in engine control units and ADAS domain controllers.
For engineers reviewing the SN74HC138QDRG4Q1 datasheet, SN74HC138QDRG4Q1 pinout, SN74HC138QDRG4Q1 application, or SN74HC138QDRG4Q1 equivalent, key selection criteria include automotive temperature range (−40°C to 125°C), three enable inputs (G1, G2A, G2B) for cascading, active-low outputs, and compatibility with LSTTL loads in safety-critical logic subsystems.
Technical Context
This device implements combinational logic decoding using standard HC CMOS technology, with three binary select inputs (A, B, C) and three enable terminals (G1 high-active, G2A/G2B low-active) that jointly determine which of eight Y0–Y7 outputs is asserted low. All outputs are active-low and open-drain compatible only when used with external pull-ups.
Propagation delay is tightly specified across VCC (2 V to 6 V) and temperature (−40°C to 125°C), with tpd ≤ 46 ns at 6 V and ≤ 54 ns at 4.5 V (CL = 50 pF). Input transition times are constrained to ≤ 400 ns at 6 V to ensure valid timing margins in synchronous memory decode trees.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2 V to 6 V - supports direct interface with 3.3 V and 5 V logic domains without level shifters. |
| tpd (Typical) | 15 ns at VCC = 5 V - enables use in high-speed memory decode paths where system access time < 25 ns. |
| Output Drive | ±4 mA at 5 V - sufficient to directly drive 10 LSTTL loads or interface with microcontroller GPIOs. |
| ICC (Max) | 80 µA - enables low-quiescent-power operation in always-on automotive modules. |
| Operating Temp | −40°C to 125°C - qualified per AEC-Q100 Grade 1 for under-hood and powertrain applications. |
| ESD Rating | 2000 V HBM, 200 V MM - meets automotive ESD robustness requirements for PCB-level handling. |
| Input Current | 1 µA max - eliminates need for input biasing in high-impedance control signal routing. |
Pinout & Package
SN74HC138QDRG4Q1 is housed in a 16-pin SOIC (D) package with 1.27-mm pitch, 10.3-mm body width, and RoHS-compliant NiPdAu lead finish. Pin 1 is located in quadrant Q1 per tape-and-reel orientation standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Enable input (active-low) | First low-enable control; must be low with G2B low and G1 high for decoder activation. |
| 2 (G2B) | Enable input (active-low) | Second low-enable control; both G2A and G2B must be low for function enable. |
| 3 (G1) | Enable input (active-high) | High-enable control; all three enables required for output selection. |
| 4 (C) | Binary select input | MSB of 3-bit address; determines Y4–Y7 vs Y0–Y3 group selection. |
| 5 (B) | Binary select input | Middle bit; combined with A and C to uniquely select one of eight outputs. |
| 6 (A) | Binary select input | LSB of address; toggling A alone switches between adjacent output pairs (e.g., Y0↔Y1). |
| 7 (Y0) | Active-low decoded output | Asserted low when A=B=C=0 and all enables satisfied; drives external LED or enable line. |
| 8 (GND) | Ground reference | Primary return path for all internal logic and output current sinks. |
| 9 (Y1) | Active-low decoded output | Asserted low when A=1, B=C=0; used for peripheral chip-select in multi-device buses. |
| 10 (Y2) | Active-low decoded output | Asserted low when A=0, B=1, C=0; commonly assigned to sensor interface enable. |
| 11 (Y3) | Active-low decoded output | Asserted low when A=B=1, C=0; supports dual-memory bank selection in boot ROM systems. |
| 12 (Y4) | Active-low decoded output | Asserted low when C=1, A=B=0; routes signals to CAN transceiver control logic. |
| 13 (Y5) | Active-low decoded output | Asserted low when C=1, A=1, B=0; enables diagnostic LED driver in dashboard MCU. |
| 14 (Y6) | Active-low decoded output | Asserted low when C=1, A=0, B=1; selects LIN bus transceiver in body control module. |
| 15 (Y7) | Active-low decoded output | Asserted low when A=B=C=1; used as watchdog reset enable in safety-monitoring circuits. |
| 16 (VCC) | Positive supply | Power rail for HC logic core; requires local 100-nF ceramic decoupling within 5 mm. |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs | Enables hierarchical decoding (e.g., 24-line via cascaded SN74HC138QDRG4Q1 devices) without external inverters. |
| Automotive qualification | AEC-Q100 Grade 1 compliance ensures reliability in engine bay and transmission control environments. |
| Low dynamic power | 85-pF power dissipation capacitance (Cpd) limits switching current in burst-mode wake-up circuits. |
| Input hysteresis free | CMOS inputs accept slow-rising control signals (e.g., from microcontroller GPIOs) without oscillation. |
| Output compatibility | Active-low outputs interface directly with TTL, CMOS, and microcontroller interrupt inputs without pull-up resistors in many cases. |
Applications
| Engine Control Unit (ECU) Memory Mapping | ADAS Domain Controller I/O Expansion |
|---|---|
|
Use Scenario: Decoding 3-bit address from MCU to select among eight flash memory banks during boot sequence. IC Role / Device Role / Timing Role: Address decoder providing sub-20-ns propagation delay to meet tight memory access timing budgets. Use Value: Eliminates need for FPGA-based address logic, reducing BOM cost and board area in compact ECU modules. |
Use Scenario: Expanding limited GPIO count on radar processor to manage 8 camera sensor power rails. IC Role / Device Role / Timing Role: Demultiplexer enabling single control line to activate individual camera power sequencers. Use Value: Reduces interconnect complexity and improves fault isolation by assigning dedicated Yx outputs per sensor rail. |
| Body Control Module (BCM) Peripheral Enable | Instrument Cluster Display Backlight Control |
|
Use Scenario: Selecting one of eight LIN transceivers for door module communication based on CAN command. IC Role / Device Role / Timing Role: Logic-level translator and selector driving LIN enable pins with precise timing alignment. Use Value: Enables deterministic multi-node LIN arbitration without software overhead in real-time BCM firmware. |
Use Scenario: Controlling eight independent LED backlight segments in TFT display using PWM-modulated enable lines. IC Role / Device Role / Timing Role: Synchronized demultiplexer accepting PWM input on G1 to modulate brightness per segment. Use Value: Achieves uniform dimming response across segments without requiring eight separate PWM channels. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT138QDRQ1 | CMOS inputs with TTL-compatible thresholds (VIH = 2 V min); identical pinout and timing. | Better noise margin in mixed-voltage 5 V systems with legacy TTL peripherals. | Select when interfacing with older 5 V TTL logic families where HC thresholds may cause marginal VIH. |
| MC74HC138ADR2G | Same logic function but rated for −55°C to 125°C; different SOIC-16 footprint (slightly wider body). | Suitable for extended-temperature industrial or aerospace deployments outside AEC-Q100 scope. | Choose when operating below −40°C or requiring ON Semiconductor's long-term supply commitment. |
Compared with SN74HC138QDRG4Q1, SN74HCT138QDRQ1 offers improved input threshold compatibility with legacy 5 V TTL, while MC74HC138ADR2G extends low-temperature capability beyond automotive spec - neither is pin-compatible without layout review due to minor package dimensional variances.
Availability
SN74HC138QDRG4Q1 is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, and body control modules requiring stable component supply across automotive production lifecycles.
Supply support for SN74HC138QDRG4Q1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for automotive, industrial, and personal electronics markets.
The SN74HC138-Q1 belongs to TI's automotive logic portfolio, engineered specifically for high-reliability decoding in memory and data-routing subsystems where AEC-Q100 qualification and sub-20-ns timing are mandatory.
FAQ
What is the maximum clock frequency supported by SN74HC138QDRG4Q1?
SN74HC138QDRG4Q1 is a combinational logic device without a clock input; it does not operate at a clock frequency. Its speed is defined by propagation delay - up to 46 ns at 6 V - making it suitable for address decoding in systems with memory access cycles ≥ 50 ns. The SN74HC138QDRG4Q1 responds asynchronously to input changes, with no setup/hold timing constraints beyond specified input transition rates.
Does SN74HC138QDRG4Q1 support 3.3 V operation?
Yes, SN74HC138QDRG4Q1 supports 3.3 V operation within its 2 V to 6 V VCC range. At 3.3 V, it delivers guaranteed VOH ≥ 3.15 V and VOL ≤ 0.26 V under 4-mA load, ensuring interoperability with 3.3 V microcontrollers and FPGAs. Input thresholds scale with VCC, maintaining noise margin across the full voltage range.
Can SN74HC138QDRG4Q1 be used as a demultiplexer?
Yes, SN74HC138QDRG4Q1 functions as a 1-to-8 demultiplexer when one enable input (e.g., G1) is used as the data input and A/B/C serve as select lines. With G2A and G2B held low, asserting G1 high routes the logic state to the selected Yx output (active-low), enabling serial-to-parallel data distribution in automotive diagnostics interfaces.
What is the thermal resistance θJA for SN74HC138QDRG4Q1?
The SOIC-16 package of SN74HC138QDRG4Q1 has a thermal resistance θJA of 73°C/W under JEDEC-standard conditions. This value assumes a two-layer PCB with 1-in² copper pour under the package; actual junction temperature rise depends on layout, airflow, and ambient conditions. For continuous operation at 125°C ambient, power dissipation should remain below 170 mW to maintain safe junction temperatures.
Is SN74HC138QDRG4Q1 pin-compatible with non-automotive variants like SN74HC138N?
No, SN74HC138QDRG4Q1 is not pin-compatible with through-hole SN74HC138N (DIP-16), though it shares identical logic functionality and pin assignments with other SOIC-16 variants like SN74HC138DR. The "Q1" suffix denotes AEC-Q100 qualification and automotive temp range, but mechanical dimensions and solder pad layout match standard SOIC-16 footprints - verified against TI's D-package drawing.
SN74HC138QDRG4Q1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HC
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 5.2mA, 5.2mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2V ~ 6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74HC138QDRG4Q1 FAQ
1.How can I place an order for SN74HC138QDRG4Q1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74HC138QDRG4Q1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74HC138QDRG4Q1 reliable?
The price and inventory of SN74HC138QDRG4Q1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HC138QDRG4Q1 is usually 5 days.
3.What payment methods are accepted for SN74HC138QDRG4Q1?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HC138QDRG4Q1 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74HC138QDRG4Q1?
SN74HC138QDRG4Q1 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74HC138QDRG4Q1 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74HC138QDRG4Q1?
For technical support, including SN74HC138QDRG4Q1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HC138QDRG4Q1 requirements.
6.How does Aetrix verify that SN74HC138QDRG4Q1 is sourced from the original manufacturer or authorized distributors?
All SN74HC138QDRG4Q1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HC138QDRG4Q1 meets industry standards.
7.What is the process for return or replacement of SN74HC138QDRG4Q1?
All SN74HC138QDRG4Q1 units undergo pre-shipment inspection (PSI). If there is an issue with SN74HC138QDRG4Q1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HC138QDRG4Q1 part is unused and in its original packaging.
Return procedure for SN74HC138QDRG4Q1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74HC138QDRG4Q1 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
