Texas Instruments SN74HC367DT

Overview

SN74HC367DT from Texas Instruments is a hex noninverting buffer/line driver with 3-state outputs, organized as two independent banks (4-channel + 2-channel), each controlled by its own active-low output-enable pin (1OE, 2OE). It operates from 2 V to 6 V, delivers ±6 mA output drive at 5 V, exhibits typical propagation delay of 10 ns, and draws ≤80 µA ICC - used in memory address buffering, bus interfacing, and clock distribution systems.

For engineers reviewing the SN74HC367DT datasheet, SN74HC367DT pinout, SN74HC367DT application, or SN74HC367DT equivalent, this page provides verified functional architecture, SOIC-16 package mapping, 3-state timing behavior, bus-driving capability, and validated alternative options for industrial logic interface design.

Technical Context

The SN74HC367DT implements dual-bank 3-state logic: Bank 1 (pins 1–10) contains four buffers (1A1→1Y1 through 1A4→1Y4) enabled by 1OE (pin 1); Bank 2 (pins 11–15) contains two buffers (2A1→2Y1, 2A2→2Y2) enabled by 2OE (pin 15). Each output enters high-impedance state when its OE is high.

It uses silicon-gate CMOS technology, supports LSTTL load compatibility (up to 15 loads), features true (noninverting) outputs, and maintains rail-to-rail output swing (VOH ≥ VCC − 0.1 V, VOL ≤ 0.1 V at 4.5 V) across its full 2–6 V supply range.

Key Specifications

Pinout & Package

SN74HC367DT is supplied in a 16-pin SOIC (D) package measuring 9.90 mm × 3.90 mm, with standard 1.27 mm lead pitch and gull-wing leads. The package is RoHS-compliant, moisture sensitivity level 1, and rated for reflow up to 260 °C.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex 3-state buffer applications.

Compared with SN74HC367DT, SN74HCT367N offers guaranteed TTL input compatibility at 5 V, while SN74LVC367APWR delivers superior speed and drive at 3.3 V but sacrifices 5 V bus interoperability - selection depends on system voltage architecture and legacy interface requirements.

Availability

SN74HC367DT is available at Aetrix Electronics and suitable for memory address buffering, microcontroller bus interfacing, and industrial I/O expansion requiring stable component supply and long-term industrial lifecycle support.

Supply support for SN74HC367DT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of heritage in industry-standard logic families.

The SN74HC367DT belongs to TI's 74HC high-speed CMOS logic product line, engineered for reliable 3-state bus interface, memory addressing, and clock distribution in commercial and industrial equipment.

FAQ

What is the function of the two output-enable pins on the SN74HC367DT?

The SN74HC367DT has two independent active-low output-enable pins: 1OE (pin 1) controls the four buffers in Bank 1 (1Y1–1Y4), and 2OE (pin 15) controls the two buffers in Bank 2 (2Y1–2Y2). When either OE is high, its associated outputs enter high-impedance state - enabling flexible bus partitioning, such as isolating address versus control lines. This architecture is integral to the SN74HC367DT's role in multi-segment digital interfaces.

Can the SN74HC367DT operate reliably at 3.3 V supply voltage?

Yes, the SN74HC367DT is fully specified for operation from 2 V to 6 V, including 3.3 V. At VCC = 3.3 V, it delivers ≥±4 mA output drive, maintains VIH ≤ 2.0 V and VIL ≥ 0.99 V, and achieves typical propagation delay of ~15 ns (CL = 50 pF). All DC and switching parameters in the official TI datasheet SCLS309E are validated across this range, confirming robust 3.3 V compatibility for the SN74HC367DT.

Is the SN74HC367DT pin-compatible with other 74HC367 variants like SN74HC367N or SN74HC367DR?

Yes, the SN74HC367DT shares identical pinout, logic function, and electrical specifications with all 74HC367 variants (e.g., SN74HC367N, SN74HC367DR, SN74HC367PWR) - differences are limited to package type (SOIC vs PDIP vs TSSOP), packaging format (tube vs tape-and-reel), and RoHS status. The SN74HC367DT's SOIC-16 footprint and signal mapping match the functional diagram in TI's SCLS309E datasheet, ensuring drop-in replacement where package mounting permits.

What is the maximum capacitive load the SN74HC367DT can drive while maintaining specified timing?

The SN74HC367DT's switching characteristics are characterized at CL = 50 pF and CL = 150 pF. At VCC = 4.5 V and TA = 25 °C, tpd increases from 19 ns (50 pF) to 24 ns (150 pF); transition time (tt) rises from 12 ns to 15 ns. For reliable timing compliance, keep total load (including trace capacitance, input capacitance of driven devices, and probe effects) ≤150 pF. Exceeding this may degrade setup/hold margins in high-speed bus applications using the SN74HC367DT.

Does the SN74HC367DT require external pull-up or pull-down resistors on unused inputs?

Yes - all unused inputs of the SN74HC367DT must be tied to VCC or GND to prevent floating states that cause excessive ICC, oscillation, or ESD susceptibility. TI's datasheet (Section 5.2 note) mandates this practice. For example, if only three of four Bank 1 inputs are used, the fourth (e.g., 1A4) must connect to VCC or GND - not left open. This requirement applies universally across all SN74HC367DT configurations to ensure predictable operation and reliability.