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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Texas Instruments SN74HC367N

Name: SN74HC367N
Brand: Texas Instruments
SKU: SN74HC367N
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74HC367N

Manufacturer:: Texas Instruments

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: SN74HC367N.pdf

Description:: IC BUFFER NON-INVERT 6V 16DIP

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Product details

Overview

SN74HC367N from Texas Instruments is a hex buffer and line driver IC with 3-state outputs, organized as two independent banks (4-channel + 2-channel), each controlled by its own active-low output-enable pin (1OE, 2OE). It operates from 2 V to 6 V, delivers ±6 mA output drive at 5 V, exhibits typical propagation delay of 10 ns, and supports bus interfacing in memory address buffering and clock distribution systems.

For engineers reviewing the SN74HC367N datasheet, SN74HC367N pinout, SN74HC367N application, or SN74HC367N equivalent, this device is selected for high-density 3-state bus driving where low power (80 µA max ICC), true (non-inverting) logic, and LSTTL-load compatibility (up to 15 loads) are required in industrial and embedded control designs.

Technical Context

The SN74HC367N implements CMOS-based hex buffering with dual independent 3-state control: Bank 1 (pins 1A1–1Y4, enabled by 1OE) contains four drivers; Bank 2 (pins 2A1–2Y2, enabled by 2OE) contains two drivers. Each output transitions to high-impedance when its respective OE is high.

It features true (non-inverting) output logic, input thresholds scaled to VCC (VIH = 0.7×VCC, VIL = 0.3×VCC), and guaranteed operation across −40°C to +85°C. Electrical behavior is defined under CL = 50 pF load, with tpd = 10 ns (typ), ten = 24 ns (typ), and tt = 13 ns (typ) at VCC = 6 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage Range	2 V to 6 V - enables direct interface with 3.3 V and 5 V logic families without level translation.
Output Drive Strength	±6 mA at 5 V - sufficient to drive 15 LSTTL loads or terminate short PCB traces on shared buses.
Propagation Delay	10 ns (typ) at VCC = 6 V, CL = 50 pF - supports reliable timing in sub-100 MHz digital control paths.
Quiescent Current	80 µA max ICC - ensures minimal standby power in battery-backed or energy-sensitive systems.
Input Leakage Current	±1 µA max - prevents unintended logic state shifts when inputs are tied to pull-up/pull-down resistors.
3-State Enable/Disable Time	ten = 24 ns, tdis = 41 ns (typ) at VCC = 6 V - allows precise bus arbitration timing in multi-master configurations.
Operating Temperature	−40°C to +85°C - qualified for industrial-grade embedded applications including PLC I/O modules and motor controllers.

Pinout & Package

SN74HC367N is supplied in a 16-pin plastic dual in-line package (PDIP), body size 19.31 mm × 6.35 mm, with through-hole mounting and standard 0.3-inch row spacing.

Pin/Terminal	Circuit Role	Design Meaning
1	1OE	Active-low output enable for Bank 1 (1A1–1Y4); drives all four outputs into high-Z when high.
2	1A1	Input for first buffer in Bank 1; non-inverted signal passes to 1Y1 when 1OE is low.
3	1Y1	True (non-inverting) output corresponding to 1A1; high-impedance when 1OE is high.
4	1A2	Input for second buffer in Bank 1; routed to 1Y2 when 1OE is low.
5	1Y2	True output for 1A2; electrically isolated from other outputs during 3-state mode.
6	1A3	Input for third buffer in Bank 1; functional only when 1OE is asserted low.
7	1Y3	True output for 1A3; shares no internal path with Bank 2 outputs.
8	GND	Power ground reference for all logic and output stages; must be low-impedance connection.
9	1A4	Input for fourth buffer in Bank 1; enables full 4-channel buffering under single enable control.
10	1Y4	True output for 1A4; completes Bank 1's quad-driver capability.
11	2Y1	True output for 2A1 in Bank 2; independently controlled by 2OE (pin 15).
12	2A1	Input for first buffer in Bank 2; isolated from Bank 1 signal paths.
13	2Y2	True output for 2A2; provides dual-channel buffering with separate enable.
14	2A2	Input for second buffer in Bank 2; supports independent 2-signal routing.
15	2OE	Active-low output enable for Bank 2 (2A1–2Y2); independent of 1OE for flexible bus partitioning.
16	VCC	Positive supply rail (2–6 V); requires local 0.1 µF bypass capacitor per TI layout guidelines.

Key Features

Feature	Design Value
Wide supply range (2–6 V)	Eliminates need for dedicated voltage regulators when interfacing mixed-voltage subsystems (e.g., 3.3 V MCU to 5 V peripheral bus).
High-current 3-state outputs	±6 mA drive at 5 V ensures robust signal integrity across loaded backplanes or long trace runs without external buffers.
Low power consumption	80 µA max ICC reduces thermal load and extends runtime in always-on industrial monitoring nodes.
True (non-inverting) outputs	Maintains signal polarity end-to-end-critical for address/data bus mirroring and clock fanout without logic inversion errors.
Dual independent output-enable controls	Enables selective activation of 4-line vs. 2-line banks-ideal for dynamic bus segmentation in programmable logic controllers.

Applications

Memory Address Buffering	Microcontroller Bus Expansion
Use Scenario: Driving 16-bit address lines from an MCU to multiple SRAM or flash devices sharing a common data bus. IC Role / Device Role / Timing Role: SN74HC367N acts as a non-inverting 3-state address latch buffer, isolating address signals during data read/write cycles. Use Value: Prevents bus contention via independent 1OE/2OE control, while 15-LSTTL load drive ensures signal integrity across 4+ memory chips.	Use Scenario: Expanding GPIO count of an ARM Cortex-M0+ microcontroller to manage discrete I/O peripherals (LEDs, relays, sensors). IC Role / Device Role / Timing Role: SN74HC367N serves as a general-purpose 3-state output expander, enabling time-multiplexed control of multiple loads. Use Value: Dual bank architecture allows simultaneous control of 4 status indicators and 2 relay drivers with independent enable timing.
Industrial Serial Bus Interface	Legacy System Signal Conditioning
Use Scenario: Level-shifting and buffering RS-485 transceiver control signals (DE/RE) in a noisy factory-floor CAN-to-RS-485 gateway. IC Role / Device Role / Timing Role: SN74HC367N conditions TTL-level enable signals before driving RS-485 driver/receiver ICs with precise timing margins. Use Value: 10 ns propagation delay and 24 ns enable time ensure setup/hold compliance for RS-485 half-duplex switching at 115.2 kbps.	Use Scenario: Interfacing modern 3.3 V FPGAs to legacy 5 V parallel EEPROMs or LCD controllers in retro equipment upgrades. IC Role / Device Role / Timing Role: SN74HC367N functions as a bidirectional voltage-tolerant buffer, translating logic levels while maintaining signal polarity. Use Value: 2–6 V supply range permits direct 3.3 V operation with 5 V-tolerant outputs, avoiding discrete level-shifters and reducing BOM count.

Memory Address Buffering

Microcontroller Bus Expansion

Use Scenario: Driving 16-bit address lines from an MCU to multiple SRAM or flash devices sharing a common data bus.

IC Role / Device Role / Timing Role: SN74HC367N acts as a non-inverting 3-state address latch buffer, isolating address signals during data read/write cycles.

Use Value: Prevents bus contention via independent 1OE/2OE control, while 15-LSTTL load drive ensures signal integrity across 4+ memory chips.

Use Scenario: Expanding GPIO count of an ARM Cortex-M0+ microcontroller to manage discrete I/O peripherals (LEDs, relays, sensors).

IC Role / Device Role / Timing Role: SN74HC367N serves as a general-purpose 3-state output expander, enabling time-multiplexed control of multiple loads.

Use Value: Dual bank architecture allows simultaneous control of 4 status indicators and 2 relay drivers with independent enable timing.

Industrial Serial Bus Interface

Legacy System Signal Conditioning

Use Scenario: Level-shifting and buffering RS-485 transceiver control signals (DE/RE) in a noisy factory-floor CAN-to-RS-485 gateway.

IC Role / Device Role / Timing Role: SN74HC367N conditions TTL-level enable signals before driving RS-485 driver/receiver ICs with precise timing margins.

Use Value: 10 ns propagation delay and 24 ns enable time ensure setup/hold compliance for RS-485 half-duplex switching at 115.2 kbps.

Use Scenario: Interfacing modern 3.3 V FPGAs to legacy 5 V parallel EEPROMs or LCD controllers in retro equipment upgrades.

IC Role / Device Role / Timing Role: SN74HC367N functions as a bidirectional voltage-tolerant buffer, translating logic levels while maintaining signal polarity.

Use Value: 2–6 V supply range permits direct 3.3 V operation with 5 V-tolerant outputs, avoiding discrete level-shifters and reducing BOM count.

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex buffer with 3-state output applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HCT367N	CMOS input thresholds replaced with TTL-compatible thresholds (VIH = 2.0 V min at VCC = 4.5 V); otherwise identical pinout, timing, and drive.	Better suited for direct interfacing with legacy 5 V TTL logic without pull-ups; less suitable for mixed 3.3 V/5 V systems requiring CMOS threshold scaling.	Select SN74HCT367N only when driving or receiving from standard TTL outputs; retain SN74HC367N for CMOS-native or wide-VCC designs.
74LCX367M	Lower VCC range (2.0–3.6 V), higher speed (tpd = 5.5 ns typ at 3.3 V), and 5 V-tolerant inputs; different pinout (SOIC-16 only, no PDIP option).	Optimized for 3.3 V-only systems requiring faster bus turnaround; incompatible with 5 V operation or through-hole assembly.	Choose 74LCX367M for high-speed 3.3 V FPGA I/O expansion; use SN74HC367N when 5 V support, PDIP packaging, or industrial temp range is mandatory.

Compared with SN74HCT367N and 74LCX367M, the SN74HC367N uniquely balances wide supply flexibility (2–6 V), industrial temperature rating (−40°C to +85°C), PDIP availability, and CMOS input compatibility-making it the default choice for general-purpose 3-state buffering in mixed-voltage industrial hardware.

Availability

SN74HC367N is available at Aetrix Electronics and suitable for memory address buffering, microcontroller bus expansion, and industrial serial interface applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant through-hole packaging.

Supply support for SN74HC367N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in industrial, automotive, and communications markets.

The SN74HC367N belongs to TI's 74HC logic family-designed for high-noise-immunity, low-power, pin-compatible replacements of legacy TTL logic in industrial control, instrumentation, and legacy system upgrades.

FAQ

What is the maximum operating voltage for the SN74HC367N?

The SN74HC367N supports a maximum supply voltage of 6 V, with absolute maximum rating at 7 V. Operation above 6 V violates recommended conditions and risks parametric shift or accelerated wear-out. The device is fully specified from 2 V to 6 V, making it compatible with both 3.3 V and 5 V systems without external regulation.

Does the SN74HC367N support 3.3 V operation with 5 V-tolerant inputs?

No-the SN74HC367N does not feature 5 V-tolerant inputs. Its input voltage limits are rail-to-rail (0 V to VCC), and VIH/VIL thresholds scale with VCC (e.g., VIH = 3.15 V min at VCC = 4.5 V). When operated at 3.3 V, inputs must remain within 0–3.3 V; applying 5 V signals will exceed absolute maximum ratings and may cause damage.

How are the two output-enable pins (1OE and 2OE) used in practice?

1OE controls the four buffers in Bank 1 (1A1–1Y4), while 2OE independently controls the two buffers in Bank 2 (2A1–2Y2). This allows selective activation-for example, using 1OE to gate address lines and 2OE to control chip-select strobes-enabling time-multiplexed bus access or partial resource isolation in complex I/O architectures.

Can unused inputs on the SN74HC367N be left floating?

No-TI explicitly requires all unused inputs to be tied to VCC or GND. Floating CMOS inputs induce shoot-through current, increase power consumption, cause erratic output states, and raise EMI susceptibility. For SN74HC367N, tie unconnected A-inputs to GND (for logic-low default) or VCC (for logic-high default), per the function table and SCBA004 application report.

What is the thermal resistance (RθJA) of the SN74HC367N in PDIP package?

The SN74HC367N in PDIP (N) package has a junction-to-ambient thermal resistance (RθJA) of 67°C/W, as specified in the Thermal Information table. This value assumes standard JEDEC 2-layer board conditions; actual performance improves with added copper pour or airflow, and degrades with dense component placement or lack of thermal vias.

SN74HC367N Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74HC

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Bulk

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 2, 4 (Hex)

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 7.8mA, 7.8mA

Voltage - Supply:: 2V ~ 6V

Operating Temperature:: -40°C ~ 85°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-PDIP

SN74HC367N FAQ

1.How can I place an order for SN74HC367N through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74HC367N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74HC367N reliable?

The price and inventory of SN74HC367N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HC367N is usually 5 days.

3.What payment methods are accepted for SN74HC367N?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HC367N transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74HC367N?

SN74HC367N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74HC367N order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74HC367N?

For technical support, including SN74HC367N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HC367N requirements.

6.How does Aetrix verify that SN74HC367N is sourced from the original manufacturer or authorized distributors?

All SN74HC367N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HC367N meets industry standards.

7.What is the process for return or replacement of SN74HC367N?

All SN74HC367N units undergo pre-shipment inspection (PSI). If there is an issue with SN74HC367N, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74HC367N part is unused and in its original packaging.

Return procedure for SN74HC367N:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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