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Texas Instruments SN74HCT138DT
- Part No.:
- SN74HCT138DT
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74HCT138DT.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:662
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Product details
Overview
SN74HCT138DT from Texas Instruments is a 3-line to 8-line decoder/demultiplexer in SOIC-16 package, operating at 4.5 V–5.5 V supply, with 17 ns typical propagation delay (at 5.5 V), ±4 mA output drive, and TTL-compatible inputs. It serves as a high-speed memory address decoder or data routing switch in embedded control and industrial logic systems.
For engineers reviewing the SN74HCT138DT datasheet, SN74HCT138DT pinout, SN74HCT138DT application, or SN74HCT138DT equivalent, this page delivers verified functional modes, enable-input cascading behavior, switching characteristics under 50-pF load, and real-world demultiplexing use cases - all grounded in TI's SCLS171F production data sheet.
Technical Context
The SN74HCT138DT implements active-low 3-to-8 decoding with three independent enable inputs (G1, G2A, G2B): one active-high (G1) and two active-low (G2A, G2B), enabling flexible hierarchical expansion without external inverters. Its function table defines eight mutually exclusive low-active outputs (Y0–Y7), each asserted only when all enables are satisfied and select lines match.
Designed for memory-decoding applications, it achieves sub-access-time system delay when paired with fast-enable memories: propagation delay (tpd ≤ 34 ns max at 5.5 V) and enable-to-output delay (≤ 38 ns) are both less than typical SRAM access times. Input hold current is limited to ±1 µA max, supporting clean TTL-level interfacing without loading legacy drivers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - ensures compatibility with standard 5-V TTL and mixed-voltage logic systems. |
| Propagation Delay (tpd) | 17 ns typical at 5.5 V, CL = 50 pF - enables synchronization with >20 MHz address strobes in memory subsystems. |
| Output Drive | ±4 mA at 5 V - directly interfaces with 10 LSTTL loads without buffer stages. |
| Input Compatibility | TTL-voltage compatible (VIH = 2 V min, VIL = 0.8 V max) - accepts standard 5-V TTL logic levels without level-shifting. |
| Quiescent Current (ICC) | 80 µA max - supports low-static-power operation in always-on control logic. |
| Operating Temperature | -40 °C to +85 °C - qualified for industrial-grade embedded applications. |
Pinout & Package
SN74HCT138DT uses a 16-pin SOIC (D) package with nominal body size 9.90 mm × 3.90 mm and 1.27-mm lead pitch. Pin 1 is located at the top-left corner adjacent to the index notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Active-low enable input | Must be low to activate decoding; used with G2B and G1 for 3-input cascade control. |
| 2 (G2B) | Active-low enable input | Second active-low enable; both G2A and G2B must be low for device enable. |
| 3 (G1) | Active-high enable input | Must be high to activate; simplifies multi-chip decoding trees using single inverter per stage. |
| 4 (C) | MSB address input | Binary select line C; combined with B and A to determine which Yx output goes low. |
| 5 (B) | Address input | Mid-bit address input; forms 3-bit binary code with C and A. |
| 6 (A) | LSB address input | Least-significant address bit; completes 3-bit selection for 1-of-8 decode. |
| 7 (Y0) | Active-low decoded output | Asserted low when CBA = 000 and all enables active; drives memory chip-select or peripheral enable. |
| 8 (GND) | Ground reference | Power return path; requires local 0.1-µF bypass capacitor per TI layout guidelines. |
| 9 (Y1) | Active-low decoded output | Asserted low when CBA = 001; provides discrete channel selection in demux mode. |
| 10 (Y2) | Active-low decoded output | Asserted low when CBA = 010; supports parallel peripheral addressing in microcontroller I/O expansion. |
| 11 (Y3) | Active-low decoded output | Asserted low when CBA = 011; used in 4-device cascaded 24-line decoder configurations. |
| 12 (Y4) | Active-low decoded output | Asserted low when CBA = 100; enables selective activation of memory banks or sensor groups. |
| 13 (Y5) | Active-low decoded output | Asserted low when CBA = 101; supports dual-bank flash memory selection with shared data bus. |
| 14 (Y6) | Active-low decoded output | Asserted low when CBA = 110; used in FPGA configuration interface address decoding. |
| 15 (Y7) | Active-low decoded output | Asserted low when CBA = 111; final output for full 3-bit decode space; terminates cascaded chains. |
| 16 (VCC) | Positive supply | 5-V nominal supply; requires dedicated 0.1-µF ceramic bypass capacitor placed near pin. |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs (G1, G2A, G2B) | Enables direct 24-line decoding without external inverters and 32-line with only one inverter - reduces gate count and board area. |
| 17 ns typical tpd at 5.5 V | Meets timing budgets for 20+ MHz address strobes in SRAM/ROM subsystems without adding pipeline stages. |
| TTL-compatible input thresholds | Accepts legacy 5-V TTL outputs directly (VIH ≥ 2 V, VIL ≤ 0.8 V), eliminating level translators in mixed-logic designs. |
| ±4-mA output drive capability | Drives 10 LSTTL loads per output - sufficient for direct chip-select assertion on multiple memory devices. |
| Low ICC (80 µA max) | Minimizes static power in always-enabled control logic blocks, critical for battery-backed or energy-sensitive systems. |
Applications
| Memory Address Decoding | Data Routing in Industrial PLCs |
|---|---|
Use Scenario: Selecting one of eight SRAM chips in a 64-kB memory bank using A15–A13 address bits. IC Role / Device Role / Timing Role: 3-to-8 decoder mapping upper address bits to individual chip-select lines with <34 ns enable-to-output delay. Use Value: Eliminates cumulative delay from discrete NAND gates, ensuring memory access time remains within 70 ns spec. | Use Scenario: Distributing a serial command stream from an MCU UART to eight field I/O modules via parallel control lines. IC Role / Device Role / Timing Role: Demultiplexer converting 3-bit module ID into one-of-eight active-low enable signals synchronized to data framing. Use Value: Enables deterministic, glitch-free module selection without software overhead or additional GPIO resources. |
| Microcontroller I/O Expansion | FPGA Configuration Interface |
Use Scenario: Expanding 3 GPIO pins on an 8-bit MCU to control eight discrete peripherals (LEDs, relays, sensors). IC Role / Device Role / Timing Role: Addressable output selector where A/B/C pins act as dynamic address bus and enables tie to fixed control logic. Use Value: Reduces required MCU port pins by 5 while maintaining full independent control over all eight outputs. | Use Scenario: Decoding configuration address lines (ADDR[2:0]) to select one of eight FPGA configuration PROMs during boot. IC Role / Device Role / Timing Role: Boot-time address decoder asserting CS# on correct PROM before FPGA initiates read sequence. Use Value: Guarantees setup time margin (>15 ns) between PROM selection and first clock edge, preventing configuration failure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HCT138N | Same logic function and electrical specs; PDIP-16 package (19.31 mm × 6.35 mm), through-hole mount, RoHS-compliant, -40°C to +85°C. | Suitable for prototyping, manual assembly, or legacy through-hole PCBs where SOIC reflow is unavailable. | Select SN74HCT138N for breadboarding, educational labs, or repair of legacy industrial controllers with DIP footprints. |
| SN74LV138A | Lower voltage operation (2.0 V–5.5 V); 19 ns typical tpd at 3.3 V; 6 mA drive; CMOS input structure (II < 1 µA). | Better suited for mixed 3.3-V/5-V systems or ultra-low-power standby modes where HCT's TTL input bias is unnecessary. | Choose SN74LV138A when migrating to 3.3-V core logic or requiring wider VCC range without sacrificing speed or drive strength. |
Compared with SN74HCT138N, SN74HCT138DT offers identical logic and timing but in surface-mount SOIC for automated assembly; versus SN74LV138A, it trades 3.3-V compatibility for guaranteed TTL input robustness and tighter noise margins in noisy 5-V environments.
Availability
SN74HCT138DT is available at Aetrix Electronics and suitable for industrial control panels, legacy memory subsystems, and microcontroller-based I/O expanders requiring stable component supply across long-lifecycle programs.
Supply support for SN74HCT138DT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
The SN74HCT138DT belongs to TI's 74HCT logic family, engineered for TTL-compatible operation at 5 V with high noise immunity and low power - specifically targeting memory decoding and data routing in cost-sensitive, high-reliability embedded systems.
FAQ
What is the maximum propagation delay of SN74HCT138DT at 5.5 V?
The maximum propagation delay (tpd) of SN74HCT138DT is 34 ns at VCC = 5.5 V and TA = 25°C with CL = 50 pF, as specified in the Switching Characteristics table of TI's SCLS171F datasheet. This value applies to both address-to-output (A/B/C → Yx) and enable-to-output (G1/G2A/G2B → Yx) paths, ensuring predictable timing in memory decode chains where SN74HCT138DT is deployed.
Does SN74HCT138DT support cascading with other decoders?
Yes, SN74HCT138DT supports cascading via its three enable inputs: G1 (active-high), G2A, and G2B (both active-low). By connecting outputs of one SN74HCT138DT to enables of others, designers can build 24-line decoders without external inverters or 32-line decoders with just one inverter - a capability explicitly documented in TI's functional description and verified in the device's truth table.
Can SN74HCT138DT operate with a 3.3-V supply?
No, SN74HCT138DT is not rated for 3.3-V operation. Its recommended operating conditions specify VCC = 4.5 V to 5.5 V only. Attempting to power SN74HCT138DT at 3.3 V may result in undefined output states, excessive ICC, or failure to meet VIH/VIL thresholds. For 3.3-V systems, TI recommends SN74LV138A as a functionally equivalent alternative.
What is the output drive capability of SN74HCT138DT?
SN74HCT138DT provides ±4 mA output drive per Yx pin at VCC = 5 V, enabling direct interface with up to 10 LSTTL loads. This is confirmed in the Electrical Characteristics table (IOH = –4 mA, VOL ≤ 0.33 V; IOL = 4 mA, VOH ≥ 3.7 V), making SN74HCT138DT suitable for driving chip-select inputs of memory ICs or enabling multiple peripheral devices without external buffers.
Is SN74HCT138DT pin-compatible with other 74HCT138 variants?
Yes, SN74HCT138DT shares identical pinout and function with all 16-pin 74HCT138 variants including SN74HCT138N (PDIP), SN74HCT138NS (SO), and SN74HCT138PW (TSSOP), as confirmed by TI's Pin Configuration and Functions section. All adhere to the same SOIC-16 (D), PDIP-16 (N), SOP-16 (NS), and TSSOP-16 (PW) footprints with matching signal assignments and power/ground locations.
SN74HCT138DT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HCT
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 4mA, 4mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74HCT138DT FAQ
1.How can I place an order for SN74HCT138DT through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74HCT138DT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74HCT138DT reliable?
The price and inventory of SN74HCT138DT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HCT138DT is usually 5 days.
3.What payment methods are accepted for SN74HCT138DT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HCT138DT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74HCT138DT?
SN74HCT138DT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74HCT138DT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74HCT138DT?
For technical support, including SN74HCT138DT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HCT138DT requirements.
6.How does Aetrix verify that SN74HCT138DT is sourced from the original manufacturer or authorized distributors?
All SN74HCT138DT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HCT138DT meets industry standards.
7.What is the process for return or replacement of SN74HCT138DT?
All SN74HCT138DT units undergo pre-shipment inspection (PSI). If there is an issue with SN74HCT138DT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HCT138DT part is unused and in its original packaging.
Return procedure for SN74HCT138DT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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