Texas Instruments SN74HCT138NG4
- Part No.:
- SN74HCT138NG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74HCT138NG4.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16DIP
- Quantity:
- Payment:

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Product details
Overview
SN74HCT138NG4 from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC operating at 4.5–5.5 V, delivering 17 ns typical propagation delay (tpd), ±4-mA output drive at 5 V, and low 80-µA max supply current (ICC). It features three enable inputs (two active-low, one active-high) for cascading in memory decoding and data routing systems.
For engineers reviewing the SN74HCT138NG4 datasheet, SN74HCT138NG4 pinout, SN74HCT138NG4 application, or SN74HCT138NG4 equivalent, this device is selected for high-speed address decoding in SRAM/ROM systems, bus demultiplexing in microcontroller peripherals, and logic-level signal routing where TTL-compatible inputs and LSTTL-load drive capability are required.
Technical Context
The SN74HCT138NG4 implements combinational logic decoding with binary-select inputs (A, B, C) and three independent enables (G1, G2A, G2B) that collectively determine which of eight active-low outputs (Y0–Y7) is asserted. Its architecture supports direct demultiplexing by using an enable input as a data line.
Designed for minimal system delay impact, it achieves tpd ≤ 34 ns over full temperature range (–40°C to +85°C) and interfaces directly with TTL logic families due to VIH = 2 V / VIL = 0.8 V thresholds and input compatibility with standard TTL voltage levels.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures stable operation across industrial-grade 5-V rails with margin for ripple or drop. |
| tpd (max) | 49 ns at 4.5 V - Guarantees sub-50 ns address decode latency in fast memory subsystems. |
| Output Drive | ±4 mA at 5 V - Sufficient to directly drive 10 LSTTL loads without buffering. |
| ICC (max) | 80 µA - Enables low-static-power operation in always-on control logic or battery-backed systems. |
| Input Thresholds | VIH = 2 V, VIL = 0.8 V - Matches standard TTL logic levels for seamless interfacing with legacy controllers. |
| Operating Temp | –40°C to +85°C - Qualified for commercial and industrial ambient environments. |
Pinout & Package
SN74HCT138NG4 uses a 16-pin PDIP (Plastic Dual In-line Package) with nominal body size 19.31 mm × 6.35 mm and through-hole mounting. Pin 1 is located at the top-left corner with notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Active-low enable input | Must be low to activate decoding; used with G2B and G1 for hierarchical enable control. |
| 2 (Y0) | Active-low decoded output | Asserted low when A=0, B=0, C=0 and all enables active - drives memory chip select or peripheral enable. |
| 3 (Y1) | Active-low decoded output | Asserted low for A=1, B=0, C=0 - provides discrete channel selection in 1-of-8 routing. |
| 4 (Y2) | Active-low decoded output | Asserted low for A=0, B=1, C=0 - supports modular I/O expansion via output gating. |
| 5 (Y3) | Active-low decoded output | Asserted low for A=1, B=1, C=0 - enables parallel peripheral addressing in microcontroller buses. |
| 6 (Y4) | Active-low decoded output | Asserted low for A=0, B=0, C=1 - used in segmented memory bank selection. |
| 7 (Y5) | Active-low decoded output | Asserted low for A=1, B=0, C=1 - facilitates multi-device arbitration in shared-bus systems. |
| 8 (GND) | Ground reference | Return path for all internal logic and output currents; must be low-impedance for noise immunity. |
| 9 (Y6) | Active-low decoded output | Asserted low for A=0, B=1, C=1 - supports dual-bank flash memory addressing schemes. |
| 10 (Y7) | Active-low decoded output | Asserted low for A=1, B=1, C=1 - final output for full 3-bit decode space coverage. |
| 11 (C) | Binary select input | MSB address bit for 3-bit decode; latched on rising edge of enable conditions. |
| 12 (B) | Binary select input | Middle address bit; determines quadrant of output activation within the 8-line map. |
| 13 (A) | Binary select input | LSB address bit; resolves individual line within each pair of outputs. |
| 14 (G1) | Active-high enable input | Must be high to enable function; allows OR-style cascade control with other decoders. |
| 15 (G2B) | Active-low enable input | Second active-low enable; used with G2A to form NAND-enable logic for compact expansion. |
| 16 (VCC) | Positive supply | 5-V power rail; requires local 0.1-µF bypass capacitor per TI layout guidelines. |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs | Enables 24-line decoding without external inverters and 32-line with only one inverter - reduces gate count and board area. |
| TTL-compatible inputs | Accepts standard TTL voltage thresholds (VIH = 2 V, VIL = 0.8 V), eliminating level-shifting in mixed-logic systems. |
| Low ICC (80 µA max) | Minimizes quiescent power in standby modes of embedded controllers and portable instrumentation. |
| 17 ns typical tpd | Ensures decoder delay is negligible relative to typical 55–70 ns SRAM access times - preserves system timing budget. |
| ±4-mA output drive | Directly sinks or sources current for LSTTL loads, avoiding buffer stages in address/data path critical paths. |
Applications
| Memory Address Decoding | Microcontroller Peripheral Selection |
|---|---|
Use Scenario: Selecting one of eight SRAM or ROM chips in a 64 KB memory map using A15–A13 as select lines. IC Role / Device Role / Timing Role: 3-to-8 decoder mapping upper address bits to individual chip-select (CS) signals with sub-50 ns latency. Use Value: Eliminates need for discrete NAND gates or PLD-based decoding, reducing component count and propagation uncertainty. | Use Scenario: Routing UART, SPI, and I²C peripherals from a single microcontroller port with shared address/data bus. IC Role / Device Role / Timing Role: Demultiplexer enabling one peripheral at a time via active-low CS lines synchronized to address strobes. Use Value: Provides deterministic, glitch-free peripheral activation without software overhead or timing-critical firmware delays. |
| Bus Signal Routing | Industrial I/O Expansion |
Use Scenario: Distributing a single control signal (e.g., reset or interrupt) to eight downstream modules based on configuration bits. IC Role / Device Role / Timing Role: Active-low demultiplexer using G1 as data input and A/B/C as select lines - converts serial control into parallel assertion. Use Value: Enables hardware-based broadcast control distribution with fixed, predictable delay - no CPU intervention required. | Use Scenario: Expanding digital input/output capacity in PLC backplanes where 3-bit DIP switch settings define module ID. IC Role / Device Role / Timing Role: Static decoder translating DIP-switch state into dedicated enable for isolated I/O driver ICs. Use Value: Supports hot-pluggable module identification and power sequencing without reprogramming or EEPROM lookup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS138N | Lower drive (±0.4 mA), higher ICC (36 mA), slower tpd (34 ns typ at 5 V), TTL-input-only (no CMOS-level compatibility) | Requires stricter 5-V supply regulation; unsuitable for mixed-voltage or low-power systems | Choose only if legacy LS-TTL system compatibility is mandatory and power/latency budgets allow. |
| SN74HC138N | Wider VCC range (2–6 V), lower drive (±4 mA same), higher input capacitance (10 pF), identical pinout and logic function | Supports 3.3-V logic domains but lacks TTL input threshold compatibility - may require level translation with 5-V systems | Prefer for new 3.3-V designs; avoid in existing 5-V TTL environments unless input thresholds are verified. |
Compared with SN74LS138N and SN74HC138N, the SN74HCT138NG4 uniquely balances TTL input compatibility, 5-V CMOS power efficiency, and sub-50 ns speed - making it the optimal choice for upgrading legacy 5-V systems without redesigning interface logic or supply architecture.
Availability
SN74HCT138NG4 is available at Aetrix Electronics and suitable for memory decoding, microcontroller peripheral selection, and industrial I/O expansion requiring stable component supply, long-term manufacturability, and RoHS-compliant through-hole packaging.
Supply support for SN74HCT138NG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 50 years of innovation in industrial, automotive, and communications markets.
The SN74HCT138NG4 belongs to TI's HCT (High-Speed CMOS TTL-compatible) logic family, engineered specifically for drop-in replacement of legacy 74LS devices in 5-V systems while delivering lower power and improved noise immunity.
FAQ
What is the maximum propagation delay of the SN74HCT138NG4 under worst-case conditions?
The SN74HCT138NG4 has a maximum propagation delay (tpd) of 49 ns at VCC = 4.5 V and TA = 25°C, and 54 ns at VCC = 4.5 V over full operating temperature (–40°C to +85°C), per TI's SCLS171F datasheet Section 5.5. This ensures reliable timing closure in high-speed memory decode paths where total system delay must remain below 70 ns.
Can the SN74HCT138NG4 operate with a 3.3-V supply?
No, the SN74HCT138NG4 is not rated for 3.3-V operation. Its recommended VCC range is strictly 4.5 V to 5.5 V per Section 5.2 of the datasheet. Applying 3.3 V may result in undefined output states, increased ICC, or failure to meet VIH/VIL thresholds - use SN74HC138N instead for 3.3-V systems.
How many LSTTL loads can the SN74HCT138NG4 drive per output?
The SN74HCT138NG4 can drive up to 10 LSTTL loads per output, as specified in the Features section and confirmed by its ±4-mA output drive capability at 5 V. This matches the standard LSTTL unit load definition (IIL = –0.4 mA, IIH = 20 µA), enabling direct fanout without buffers in legacy TTL-based systems.
Is the SN74HCT138NG4 pin-compatible with the SN74LS138N?
Yes, the SN74HCT138NG4 is pin-compatible and functionally equivalent to the SN74LS138N in the 16-pin PDIP package, sharing identical pinout, terminal functions, and truth table behavior. However, SN74HCT138NG4 offers lower power (80 µA vs. 36 mA ICC), faster speed (17 ns vs. 34 ns tpd), and TTL-compatible inputs - making it a direct upgrade.
Does the SN74HCT138NG4 require external pull-up resistors on its outputs?
No, the SN74HCT138NG4 does not require external pull-up resistors. Its outputs are push-pull (totem-pole), capable of actively driving both high and low logic states. Pull-ups would conflict with the internal output structure and risk excessive current draw - outputs are designed to directly interface with LSTTL inputs or CMOS loads.
SN74HCT138NG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HCT
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Discontinued at Digi-Key
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 4mA, 4mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
SN74HCT138NG4 FAQ
1.How can I place an order for SN74HCT138NG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74HCT138NG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74HCT138NG4 reliable?
The price and inventory of SN74HCT138NG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HCT138NG4 is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74HCT138NG4?
For technical support, including SN74HCT138NG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HCT138NG4 requirements.
6.How does Aetrix verify that SN74HCT138NG4 is sourced from the original manufacturer or authorized distributors?
All SN74HCT138NG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HCT138NG4 meets industry standards.
7.What is the process for return or replacement of SN74HCT138NG4?
All SN74HCT138NG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74HCT138NG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HCT138NG4 part is unused and in its original packaging.
Return procedure for SN74HCT138NG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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