Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74HCT138NSR

Name: SN74HCT138NSR
Brand: Texas Instruments
SKU: SN74HCT138NSR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN74HCT138NSR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.209", 5.30mm Width)

Datasheet:: SN74HCT138NSR.pdf

Description:: IC DECODER/DEMUX 1 X 3:8 16SO

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:1,435

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN74HCT138NSR from Texas Instruments is a 3-line to 8-line decoder/demultiplexer operating at 4.5 V–5.5 V, featuring 17 ns typical propagation delay, ±4-mA output drive at 5 V, and TTL-compatible inputs. It implements active-low enable logic (G1, G2A, G2B) for cascading in memory address decoding and data routing systems.

For engineers reviewing the SN74HCT138NSR datasheet, SN74HCT138NSR pinout, SN74HCT138NSR application, or SN74HCT138NSR equivalent, this page delivers verified electrical specs, SOP-16 package details, functional mode truth table alignment, and real-world use cases in high-speed memory subsystems and bus demultiplexing.

Technical Context

The SN74HCT138NSR uses standard HCT CMOS logic with TTL-voltage-level inputs, enabling direct interface with legacy LS-TTL systems without level-shifting. Its three enable inputs-two active-low (G2A, G2B) and one active-high (G1)-support hierarchical decoding and allow single-chip implementation of 24-line decoders without external inverters.

Propagation delay is tightly specified across temperature (–40°C to +85°C) and supply voltage (4.5 V–5.5 V), with tpd = 17 ns (typ) at 5.5 V and CL = 50 pF. Output drive capability (±4 mA) and low ICC (80 µA max) ensure compatibility with LSTTL loads while minimizing system power overhead.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply Voltage	4.5 V to 5.5 V - Ensures stable operation across industrial-grade 5-V rails with margin for ripple and droop.
Propagation Delay (tpd)	17 ns (typ) at 5.5 V - Enables sub-20-ns address decode in fast SRAM/ROM systems without adding pipeline latency.
Output Drive	±4 mA at 5 V - Directly drives 10 LSTTL loads, eliminating need for buffer stages in legacy bus interfaces.
Input Compatibility	TTL-voltage compatible - Accepts standard 0.8 V/2.0 V VIH/VIL thresholds, interoperable with 74LS, 74ALS, and microcontroller GPIOs.
Quiescent Current (ICC)	80 µA max - Supports low-static-power designs where decoder remains enabled during standby modes.
Operating Temperature	–40°C to +85°C - Qualified for industrial ambient environments without derating or thermal management.

Pinout & Package

SOP-16 (NS) package: 6.20 mm × 5.30 mm body, 1.27 mm pitch, 2.00 mm max height, gull-wing leads, RoHS-compliant NiPdAu finish, MSL Level-1.

Pin/Terminal	Circuit Role	Design Meaning
1 (G2A)	Active-low enable input	Must be low to activate decoder; used for hierarchical enable chaining with other 'HCT138 devices.
2 (G2B)	Active-low enable input	Second low-enable; combined with G2A and G1 to gate all eight outputs simultaneously.
3 (G1)	Active-high enable input	High enables function; simplifies cascading by reducing external gate count in multi-chip decode trees.
4 (C)	MSB address input	Binary select line C; determines Y4–Y7 vs Y0–Y3 group activation when enables are asserted.
5 (B)	Address input	Mid-bit address line B; contributes to full 3-bit selection of one of eight active-low outputs.
6 (A)	LSB address input	Low-bit address line A; completes 3-bit binary decode; transitions directly control output state per truth table.
7 (GND)	Ground reference	Primary return path for logic and output currents; requires local 0.1-µF bypass capacitor per TI layout guidance.
8 (Y0)	Active-low decoded output	Asserted low when G1=H, G2A=L, G2B=L, and CBA=000; drives memory chip-select or peripheral enable lines.
9 (Y1)	Active-low decoded output	Asserted low for CBA=001; used for discrete peripheral selection in I/O expansion or memory-mapped device addressing.
10 (Y2)	Active-low decoded output	Asserted low for CBA=010; supports modular board design where each Yx controls a dedicated subsystem.
11 (Y3)	Active-low decoded output	Asserted low for CBA=011; enables time-multiplexed resource allocation in shared-bus architectures.
12 (Y4)	Active-low decoded output	Asserted low for CBA=100; isolates higher-address-space peripherals in segmented memory maps.
13 (Y5)	Active-low decoded output	Asserted low for CBA=101; provides deterministic timing for synchronous peripheral handshaking.
14 (Y6)	Active-low decoded output	Asserted low for CBA=110; supports bank-switching in FPGA configuration or flash memory partitioning.
15 (Y7)	Active-low decoded output	Asserted low for CBA=111; final output for full 3-to-8 decode; often tied to system reset or watchdog enable.
16 (VCC)	Positive supply	5-V nominal rail; requires local 0.1-µF ceramic bypass capacitor placed adjacent to pin per TI recommendation.

Key Features

Feature	Design Value
Three enable inputs	Two active-low (G2A/G2B) plus one active-high (G1) enable structure reduces external logic count in multi-chip decode trees and supports flexible data gating.
Short propagation delay	17 ns typical at 5.5 V ensures decoder delay is negligible versus memory access time, preserving system timing budgets in high-speed SRAM/ROM subsystems.
TTL-compatible inputs	VIH = 2.0 V min / VIL = 0.8 V max allows direct connection to 74LS/74ALS outputs and microcontroller GPIOs without level translation.
Low quiescent current	80 µA maximum ICC enables always-on decode functionality in battery-backed or low-power industrial controllers without significant standby drain.
Output drive strength	±4 mA at 5 V supports direct fanout to 10 LSTTL loads, eliminating need for intermediate buffers in legacy bus architectures.

Applications

Memory Address Decoding	Bus Demultiplexing
Use Scenario: Selecting one of eight SRAM chips in a 64-kB memory bank using A15–A13 as CBA inputs and chip-enable signals as Y0–Y7 outputs. IC Role / Device Role / Timing Role: Address decoder translating upper address bits into discrete chip-select lines with sub-20-ns latency. Use Value: Eliminates timing-critical glue logic; enables full memory bandwidth utilization by ensuring decode delay is less than SRAM access time.	Use Scenario: Routing a single 8-bit data bus to one of eight peripheral registers based on control register contents. IC Role / Device Role / Timing Role: Data-path demultiplexer using G1 as data strobe and CBA as channel select, with Yx driving peripheral enable pins. Use Value: Provides deterministic, glitch-free channel selection without clock-domain crossing; supports synchronous peripheral access at system clock rates.
I/O Expansion Interface	FPGA Configuration Control
Use Scenario: Expanding microcontroller GPIO count by enabling eight discrete I/O port expanders via individual Yx outputs. IC Role / Device Role / Timing Role: Enable controller asserting one Yx line per expander, synchronized to address/data setup/hold windows. Use Value: Reduces firmware complexity by mapping physical I/O banks to fixed address ranges; avoids software bit-banging delays.	Use Scenario: Selecting one of eight configuration PROMs for FPGA partial reconfiguration using FPGA GPIOs as CBA and G1/G2A/G2B. IC Role / Device Role / Timing Role: Configuration multiplexer providing isolated, noise-immune PROM selection during bitstream loading. Use Value: Enables field-upgradable FPGA logic partitions with zero risk of bus contention or misconfiguration due to precise enable isolation.

Memory Address Decoding

Bus Demultiplexing

Use Scenario: Selecting one of eight SRAM chips in a 64-kB memory bank using A15–A13 as CBA inputs and chip-enable signals as Y0–Y7 outputs.

IC Role / Device Role / Timing Role: Address decoder translating upper address bits into discrete chip-select lines with sub-20-ns latency.

Use Value: Eliminates timing-critical glue logic; enables full memory bandwidth utilization by ensuring decode delay is less than SRAM access time.

Use Scenario: Routing a single 8-bit data bus to one of eight peripheral registers based on control register contents.

IC Role / Device Role / Timing Role: Data-path demultiplexer using G1 as data strobe and CBA as channel select, with Yx driving peripheral enable pins.

Use Value: Provides deterministic, glitch-free channel selection without clock-domain crossing; supports synchronous peripheral access at system clock rates.

I/O Expansion Interface

FPGA Configuration Control

Use Scenario: Expanding microcontroller GPIO count by enabling eight discrete I/O port expanders via individual Yx outputs.

IC Role / Device Role / Timing Role: Enable controller asserting one Yx line per expander, synchronized to address/data setup/hold windows.

Use Value: Reduces firmware complexity by mapping physical I/O banks to fixed address ranges; avoids software bit-banging delays.

Use Scenario: Selecting one of eight configuration PROMs for FPGA partial reconfiguration using FPGA GPIOs as CBA and G1/G2A/G2B.

IC Role / Device Role / Timing Role: Configuration multiplexer providing isolated, noise-immune PROM selection during bitstream loading.

Use Value: Enables field-upgradable FPGA logic partitions with zero risk of bus contention or misconfiguration due to precise enable isolation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HC138N	CMOS input thresholds (VIH = 3.15 V min), lower drive (±4 mA still valid), but no TTL compatibility - requires level-shifting with LS-TTL sources.	Best suited for pure CMOS systems; unsuitable for mixed-logic designs with legacy TTL outputs.	Select SN74HC138N only when interfacing exclusively with HC/HCT or modern MCU GPIOs with >3.15 V VIH.
74ACT138SCX	Faster tpd = 9.5 ns (typ), higher drive (±24 mA), 5-V-only supply (4.5–5.5 V same), but higher ICC (4 µA typ) and no industrial temp grade.	Preferred for ultra-low-latency applications like high-speed test equipment; not rated for –40°C operation.	Choose 74ACT138SCX when sub-10-ns decode is mandatory and ambient temperature stays above –40°C.

Compared with SN74HC138N and 74ACT138SCX, the SN74HCT138NSR uniquely balances TTL compatibility, industrial temperature range, and 17-ns performance - making it the default choice for legacy-compatible embedded systems requiring robust, drop-in decode functionality.

Availability

SN74HCT138NSR is available at Aetrix Electronics and suitable for memory address decoding, bus demultiplexing, I/O expansion, and FPGA configuration control requiring stable component supply and long-term industrial availability.

Supply support for SN74HCT138NSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with over 90 years of innovation in industrial, automotive, and communications markets.

The SN74HCT138NSR belongs to TI's HCT logic family, engineered for seamless integration between TTL and CMOS systems - specifically targeting high-speed memory decoding and data-routing applications where voltage compatibility and timing predictability are critical.

FAQ

What is the maximum propagation delay of the SN74HCT138NSR under worst-case conditions?

The SN74HCT138NSR has a maximum propagation delay of 49 ns at VCC = 4.5 V and TA = 25°C, and 54 ns at VCC = 4.5 V across the full industrial temperature range (–40°C to +85°C), per TI's SCLS171F datasheet Section 5.5. This value applies to transitions from any address or enable input to any Y output under CL = 50 pF load conditions. The SN74HCT138NSR maintains consistent timing behavior across its specified operating window without derating.

Can the SN74HCT138NSR be used with 3.3-V microcontrollers?

No - the SN74HCT138NSR requires a 4.5 V–5.5 V supply and is designed for TTL-compatible inputs (VIH ≥ 2.0 V, VIL ≤ 0.8 V). While its inputs accept 3.3-V logic HIGH levels, the device itself cannot operate from a 3.3-V rail. To interface with 3.3-V microcontrollers, use a level-shifter or select a 3.3-V-compatible decoder such as the SN74LVC138A. The SN74HCT138NSR must be powered from 5 V to meet its specified performance and reliability.

How does the enable logic of the SN74HCT138NSR support cascading multiple devices?

With two active-low enables (G2A, G2B) and one active-high enable (G1), the SN74HCT138NSR allows hierarchical decoding: one device's Y output can drive G1 of a second device while G2A/G2B remain asserted, enabling 3-to-24 or 3-to-32 line expansion. For example, using Y0–Y2 to enable three downstream SN74HCT138NSR chips achieves 24-line decoding without external inverters. This architecture is explicitly validated in TI's function table and application notes for memory subsystems.

Is the SN74HCT138NSR pin-compatible with other package variants of the same part number?

Yes - the SN74HCT138NSR (SOP-16) shares identical pinout and signal assignment with SN74HCT138D (SOIC-16), SN74HCT138N (PDIP-16), and SN74HCT138PW (TSSOP-16). All variants use the same 16-pin configuration defined in TI's SCLS171F datasheet Figure 4, including identical G1/G2A/G2B/C/B/A/Y0–Y7 assignments and VCC/GND locations. Mechanical dimensions differ, but PCB footprint designators and netlist connectivity are fully interchangeable.

Does the SN74HCT138NSR require external pull-up or pull-down resistors on unused inputs?

Yes - all unused inputs of the SN74HCT138NSR must be externally held at VCC or GND to prevent floating states that cause increased ICC, oscillation, or undefined outputs. TI's datasheet Section 5.2 and Application Report SCBA004 mandate this practice. For example, if only two address lines are used, tie the third (e.g., C) to GND or VCC depending on required decode pattern; never leave it unconnected. This requirement applies regardless of enable state and is critical for stable industrial operation.

SN74HCT138NSR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74HCT

Package/Case:: 16-SOIC (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: Decoder/Demultiplexer

Circuit:: 1 x 3:8

Independent Circuits:: 1

Current - Output High, Low:: 4mA, 4mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 85°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

SN74HCT138NSR FAQ

1.How can I place an order for SN74HCT138NSR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74HCT138NSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74HCT138NSR reliable?

The price and inventory of SN74HCT138NSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74HCT138NSR is usually 5 days.

3.What payment methods are accepted for SN74HCT138NSR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74HCT138NSR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74HCT138NSR?

SN74HCT138NSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74HCT138NSR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74HCT138NSR?

For technical support, including SN74HCT138NSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HCT138NSR requirements.

6.How does Aetrix verify that SN74HCT138NSR is sourced from the original manufacturer or authorized distributors?

All SN74HCT138NSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HCT138NSR meets industry standards.

7.What is the process for return or replacement of SN74HCT138NSR?

All SN74HCT138NSR units undergo pre-shipment inspection (PSI). If there is an issue with SN74HCT138NSR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74HCT138NSR part is unused and in its original packaging.

Return procedure for SN74HCT138NSR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…