Texas Instruments SN74HCT138PWRG4
- Part No.:
- SN74HCT138PWRG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74HCT138PWRG4.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74HCT138PWRG4 from Texas Instruments is a 3-line to 8-line decoder/demultiplexer in TSSOP-16 package, operating at 4.5–5.5 V with 17 ns typical propagation delay, ±4-mA output drive, and TTL-compatible inputs. It serves as a high-speed memory address decoder or data routing switch in embedded control and digital logic systems.
For engineers reviewing the SN74HCT138PWRG4 datasheet, SN74HCT138PWRG4 pinout, SN74HCT138PWRG4 application, or SN74HCT138PWRG4 equivalent, key selection criteria include propagation delay under 34 ns at 5.5 V, enable-input cascading capability, LSTTL load compatibility, and industrial temperature range (–40°C to +85°C) for reliable operation in memory subsystems and bus decoding.
Technical Context
The SN74HCT138PWRG4 implements active-low 3-to-8 decoding with three independent enable inputs (G1, G2A, G2B): one active-high and two active-low. This architecture enables seamless cascading of multiple devices without external inverters-e.g., a 24-line decoder requires no additional logic, while a 32-line implementation needs only one inverter.
Its TTL-compatible input thresholds (VIH = 2.0 V min, VIL = 0.8 V max) ensure direct interfacing with legacy 5-V logic families, and its low ICC (80 µA max) supports power-sensitive applications where static current budget is constrained.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5-V logic rails and tolerant of supply ripple up to ±0.5 V. |
| Propagation Delay (tpd) | 17 ns typ @ 5.5 V - enables use in high-speed memory decode paths where total system delay must remain below memory access time. |
| Output Drive | ±4 mA @ 5 V - sufficient to directly drive 10 LSTTL loads without buffer amplification. |
| Input Compatibility | TTL-voltage - accepts standard 0.8 V/2.0 V logic thresholds, eliminating level-shifting in mixed-logic designs. |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade embedded systems including PLC I/O modules and instrumentation controllers. |
| Quiescent Current | 80 µA max - reduces standby power in always-on control logic and battery-backed subsystems. |
Pinout & Package
TSSOP-16 package: 5.00 mm × 4.40 mm body, 0.65 mm lead pitch, 1.2 mm max height, RoHS-compliant NiPdAu lead finish, MSL Level-1 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Active-low enable input | Enables decoding only when low; used with G2B and G1 to gate all outputs simultaneously. |
| 2 (Y0) | Active-low decoded output | Asserted low when A=0, B=0, C=0 and all enables active - drives memory chip-select or peripheral enable lines. |
| 3 (Y1) | Active-low decoded output | Asserted low for A=1, B=0, C=0 - provides discrete channel selection in demultiplexing mode. |
| 4 (Y2) | Active-low decoded output | Asserted low for A=0, B=1, C=0 - supports 1-of-8 routing in data-path switching applications. |
| 5 (Y3) | Active-low decoded output | Asserted low for A=1, B=1, C=0 - used in address decoding for 8-bit peripheral banks. |
| 6 (Y4) | Active-low decoded output | Asserted low for A=0, B=0, C=1 - enables selective activation of I/O expanders or sensor interfaces. |
| 7 (Y5) | Active-low decoded output | Asserted low for A=1, B=0, C=1 - supports banked memory mapping in microcontroller-based systems. |
| 8 (Y6) | Active-low decoded output | Asserted low for A=0, B=1, C=1 - used in interrupt vector decoding or multiplexed display drivers. |
| 9 (Y7) | Active-low decoded output | Asserted low for A=1, B=1, C=1 - final output for full 3-bit address space coverage. |
| 10 (G2B) | Active-low enable input | Second active-low enable; both G2A and G2B must be low for device to respond to select inputs. |
| 11 (C) | Binary select input | MSB of 3-bit address; tied to microcontroller port bit or FPGA GPIO for dynamic address resolution. |
| 12 (B) | Binary select input | Middle bit of address; determines output group (Y0–Y3 vs Y4–Y7) when cascaded. |
| 13 (A) | Binary select input | LSB of address; selects individual output within group - critical for precise peripheral addressing. |
| 14 (G1) | Active-high enable input | Primary global enable; high enables function, low forces all outputs high - used as master strobe in synchronous systems. |
| 15 (VCC) | Power supply | 5-V supply rail; requires local 0.1-µF ceramic bypass capacitor placed adjacent to pin for noise suppression. |
| 16 (GND) | Ground reference | Logic and power ground return; must be connected to low-impedance system ground plane to maintain signal integrity. |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs | G1 (active-high), G2A/G2B (active-low) allow hierarchical decoding and eliminate need for external inverters in multi-device configurations. |
| Low propagation delay | 17 ns typical at 5.5 V ensures minimal timing overhead in memory-access-critical paths, preserving system-level timing margins. |
| TTL-compatible inputs | VIH = 2.0 V min / VIL = 0.8 V max enables direct interface with legacy 5-V microcontrollers, FPGAs, and logic families without level shifters. |
| High noise immunity | Input hysteresis and 0.4-V noise margin at 5 V reduce susceptibility to ground bounce and crosstalk in dense PCB layouts. |
| Industrial temperature range | –40°C to +85°C operation supports deployment in factory automation, motor drives, and outdoor electronics without derating. |
Applications
| Memory Address Decoding | Peripheral Multiplexing |
|---|---|
Use Scenario: Selecting one of eight SRAM or Flash memory chips in a microcontroller-based data logger. IC Role / Device Role / Timing Role: Acts as address-space partitioner, translating upper address bits into individual chip-select signals with sub-34 ns latency. Use Value: Enables deterministic memory access timing by ensuring decoder delay remains below typical 45-ns Flash access time. | Use Scenario: Routing UART, SPI, or I²C signals to eight different sensor nodes on a single PCB. IC Role / Device Role / Timing Role: Functions as a demultiplexer, using G1 as data-enable and A/B/C as channel address to route serial data streams. Use Value: Reduces component count versus discrete logic gates and avoids FPGA resource usage for simple 1:8 signal routing. |
| Interrupt Vector Selection | LED Matrix Row Driver |
Use Scenario: Prioritizing and selecting among eight interrupt sources in an industrial PLC CPU module. IC Role / Device Role / Timing Role: Generates encoded interrupt request lines to the processor's priority encoder, synchronized via G1 strobe. Use Value: Provides deterministic interrupt latency (<34 ns) and eliminates software polling overhead in real-time control loops. | Use Scenario: Driving rows of an 8×8 LED matrix in multiplexed display systems for HMI panels. IC Role / Device Role / Timing Role: Serves as row-select decoder, with Y0–Y7 sinking current to activate individual LED rows under microcontroller timing control. Use Value: Delivers ±4-mA per output to drive common-anode LED rows without external transistors, simplifying BOM and layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC138PW | CMOS version: wider VCC range (2–6 V), higher tpd (29 ns typ @ 6 V), lower drive (±4 mA still valid but slower edge rates). | Suitable for mixed-voltage systems (e.g., 3.3-V MCU with 5-V peripherals); less ideal for timing-critical 5-V memory decode. | Select SN74HC138PW only if supply voltage flexibility or lower ICC (4 µA) outweighs propagation delay requirements. |
| 74ACT138SCX | Advanced CMOS: 5-V only, faster tpd (9 ns typ), higher drive (±24 mA), higher ICC (40 mA), no TTL input compatibility. | Better for ultra-high-speed bus arbitration but requires 5-V-only design and level-shifted inputs from 3.3-V controllers. | Choose 74ACT138SCX when sub-10 ns delay is mandatory and system uses dedicated 5-V logic rails with robust power delivery. |
Compared with SN74HC138PW and 74ACT138SCX, the SN74HCT138PWRG4 uniquely balances TTL compatibility, 17-ns speed, and industrial temperature rating-making it optimal for legacy 5-V embedded systems where interoperability and timing predictability are prioritized over ultra-low power or extreme speed.
Availability
SN74HCT138PWRG4 is available at Aetrix Electronics and suitable for memory address decoding, peripheral multiplexing, interrupt vector selection, and LED matrix row driving requiring stable component supply across industrial production cycles.
Supply support for SN74HCT138PWRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and consumer applications.
The SN74HCT138PWRG4 belongs to TI's 74HCT logic family, designed specifically for high-speed memory decoding and data-routing systems requiring TTL-compatible inputs, low propagation delay, and robust industrial operation.
FAQ
What is the maximum propagation delay of the SN74HCT138PWRG4 at 5.5 V?
The maximum propagation delay of the SN74HCT138PWRG4 is 34 ns at VCC = 5.5 V and TA = 25°C, as specified in the Switching Characteristics table under "Enable → Any Y" condition. This value ensures compatibility with fast memory devices whose access times exceed 34 ns, preserving system-level timing margins in decoding paths.
Can the SN74HCT138PWRG4 operate with a 3.3-V supply?
No, the SN74HCT138PWRG4 is not rated for 3.3-V operation. Its recommended operating voltage range is strictly 4.5 V to 5.5 V. Applying 3.3 V may result in undefined output states, increased propagation delay, or failure to meet VIH/VIL thresholds-TI does not characterize or guarantee functionality below 4.5 V.
How many enable inputs does the SN74HCT138PWRG4 have, and what are their logic polarities?
The SN74HCT138PWRG4 has three enable inputs: G1 (active-high), G2A (active-low), and G2B (active-low). All three must be asserted simultaneously (G1 = high, G2A = low, G2B = low) for the decoder to respond to A/B/C inputs and drive Y0–Y7 outputs.
Is the SN74HCT138PWRG4 pin-compatible with other package variants of the same part number?
Yes, the SN74HCT138PWRG4 (TSSOP-16) shares identical pinout and electrical behavior with other 16-pin variants like SN74HCT138DRG4 (SOIC-16) and SN74HCT138NSR (SOP-16). Pin functions-including G1, G2A, G2B, A–C, Y0–Y7, VCC, and GND-are positionally identical across these packages, enabling drop-in replacement where board layout permits.
Does the SN74HCT138PWRG4 require external pull-up resistors on its outputs?
No, the SN74HCT138PWRG4 features push-pull outputs capable of actively driving both high and low logic levels. Its outputs can source up to 4 mA and sink up to 4 mA at 5 V, eliminating the need for external pull-ups in standard LSTTL-load applications. Pull-ups are only required if interfacing with open-drain systems or non-standard voltage domains.
SN74HCT138PWRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74HCT
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 4mA, 4mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
SN74HCT138PWRG4 FAQ
1.How can I place an order for SN74HCT138PWRG4 through Aetrix?
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For technical support, including SN74HCT138PWRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74HCT138PWRG4 requirements.
6.How does Aetrix verify that SN74HCT138PWRG4 is sourced from the original manufacturer or authorized distributors?
All SN74HCT138PWRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74HCT138PWRG4 meets industry standards.
7.What is the process for return or replacement of SN74HCT138PWRG4?
All SN74HCT138PWRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74HCT138PWRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74HCT138PWRG4 part is unused and in its original packaging.
Return procedure for SN74HCT138PWRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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