onsemi SN74LS02D
- Part No.:
- SN74LS02D
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS02D.pdf
- Description:
- IC GATE NOR 4CH 2-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:7,430
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Product details
Overview
SN74LS02D from Texas Instruments is a quad 2-input NOR gate logic IC in SOIC-14 package, operating over 0°C to 70°C, with typical propagation delay of 15 ns at VCC = 5 V and IOL = 8 mA, used for digital signal inversion and combinational logic in industrial control panels and legacy instrumentation interfaces.
For engineers reviewing the SN74LS02D datasheet, pinout, applications, or equivalent options, this page delivers verified electrical parameters, validated pin functions, confirmed industrial temperature-range operation, and direct substitution options for TTL-based logic redesign and obsolescence mitigation.
Technical Context
The SN74LS02D implements four independent 2-input NOR gates using low-power Schottky (LS) TTL technology, with input clamp diodes enabling compatibility with standard TTL and LSTTL families. Its output stage supports fan-out of 20 LS-TTL loads and drives up to 8 mA sink current at guaranteed VOH/VOL levels.
Logic behavior follows IEEE Std 91-1984: output is LOW only when both inputs are HIGH; all other input combinations yield HIGH output. The device requires a single 5-V supply and exhibits no internal latch-up risk under normal operating conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | LS-TTL - enables interoperability with 74LS, 74L, and 74S series while reducing power vs. standard TTL. |
| Propagation Delay | 15 ns max (tPLH/tPHL) at VCC = 5 V, CL = 15 pF - ensures timing predictability in synchronous 10–20 MHz clock domains. |
| Supply Voltage | 4.75 V to 5.25 V - matches standard TTL rail tolerance; operation outside this range invalidates AC/DC specs. |
| Output Drive | 8 mA sink / 0.4 mA source - sufficient to directly drive LEDs, relays via buffer, or interface to CMOS inputs with pull-up. |
| Input Threshold | VIH = 2.0 V min, VIL = 0.8 V max - guarantees noise margin >0.4 V against 5-V TTL logic levels. |
| Operating Temp | 0°C to +70°C - qualified for commercial-grade embedded systems, not extended or military temperature ranges. |
Pinout & Package
SN74LS02D uses a 14-pin SOIC (D) package with 1.27 mm pitch, 3.9 mm body width, and 1.75 mm max height per JEDEC MS-012AB. Pin 1 is located at the top-left corner with notch or beveled edge marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 4, 5, 8, 9, 11, 12 | NOR Gate Inputs | Eight total inputs across four gates; each pair (e.g., pins 1&2 → pin 3) forms one NOR function. |
| 3, 6, 10, 13 | NOR Gate Outputs | Active-LOW outputs; HIGH only when both associated inputs are LOW. |
| 7 | GND | Ground reference for all logic and power paths; must be low-impedance connection to minimize noise coupling. |
| 14 | VCC | +5 V supply input; decoupling capacitor (0.1 µF ceramic) required within 10 mm of this pin. |
Key Features
| Feature | Design Value |
|---|---|
| Low-Power Schottky Technology | Reduces typical supply current to 19 mA per package (vs. 45 mA for 74TTL), lowering thermal load in dense PCB layouts. |
| Standard Dual-In-Line Pinout Compatibility | SOIC-14 footprint maps identically to PDIP-14 pin numbering - enables drop-in replacement on existing land patterns with minor layout review. |
| Input Clamp Diodes | Allow safe interfacing with open-collector or high-impedance sources without external protection components. |
| Guaranteed Switching at 5 V | Validated operation across full VCC range (4.75–5.25 V); no derating needed for nominal 5-V systems. |
Applications
| Industrial Control Logic | Legacy Instrumentation Interface |
|---|---|
Use Scenario: Discrete safety interlock monitoring in PLC backplanes where redundant sensor signals must inhibit actuator activation. IC Role / Device Role / Timing Role: NOR gate implements active-LOW enable logic: output goes LOW only when both sensors report fault, triggering shutdown path. Use Value: Eliminates need for external inverters or microcontroller polling; deterministic sub-20 ns response meets SIL-2 timing constraints. | Use Scenario: Signal conditioning between analog front-end comparators and microcontroller GPIOs in benchtop multimeters. IC Role / Device Role / Timing Role: Converts open-collector comparator outputs into clean, rail-to-rail TTL-compatible logic levels for MCU interrupt inputs. Use Value: Provides noise-immune level translation without pull-up resistors or software debouncing overhead. |
| Power Sequencing Supervisor | Digital Test Fixture Logic |
Use Scenario: Monitoring multiple DC supply rails (e.g., +12 V, +5 V, +3.3 V) to assert system reset until all are stable. IC Role / Device Role / Timing Role: Each NOR gate combines two rail-good signals; final wired-OR output holds reset active until all rails meet threshold. Use Value: Achieves hardware-enforced sequencing with zero firmware dependency and <100 ns jitter. | Use Scenario: Generating pass/fail strobes in automated PCB functional testers based on parallel test vector comparisons. IC Role / Device Role / Timing Role: NOR gates perform bitwise logical negation of mismatch flags from comparator banks before latching results. Use Value: Enables real-time go/no-go decision at 10 MHz test clock rates without FPGA resource consumption. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS02DR | Same electrical specs and pinout; tape-and-reel packaging (2500 pcs) vs. tube (obsolete SN74LS02D). | Designed for automated SMT assembly; identical performance in board-level logic functions. | Select SN74LS02DR for new production runs requiring pick-and-place compatibility and volume pricing. |
| SN74LS02N | Identical logic function and DC/AC specs; PDIP-14 through-hole package with 25-piece tube packaging. | Suitable for prototyping, repair, and low-volume hand-soldered assemblies where SOIC reflow is impractical. | Choose SN74LS02N when manual assembly, socketing, or legacy through-hole board compatibility is required. |
Compared with SN74LS02D, SN74LS02DR offers modern SMT logistics support while maintaining identical timing and drive capability, whereas SN74LS02N preserves mechanical and thermal characteristics of through-hole mounting for serviceability-critical deployments.
Availability
SN74LS02D is available at Aetrix Electronics and suitable for industrial control logic, legacy instrumentation interface, power sequencing supervisor, and digital test fixture logic requiring stable component supply across long-lifecycle programs.
Supply support for SN74LS02D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog, embedded processing, and logic solutions since 1930.
The SN74LS02D belongs to TI's legacy 74LS logic family, engineered for reliable, low-power digital signal routing in commercial-grade systems where cost, simplicity, and proven interoperability outweigh advanced features like 3.3-V operation or ESD hardening.
FAQ
What is the maximum clock frequency supported by SN74LS02D?
The SN74LS02D is not a clocked device but a combinational logic IC; it has no defined clock frequency. Its usable toggle rate depends on propagation delay (15 ns max) and system loading. In practice, SN74LS02D reliably supports data path switching up to ~20 MHz in lightly loaded configurations with proper decoupling. For synchronous designs, ensure setup/hold margins exceed tPLH/tPHL values specified in the SN74LS02D datasheet.
Can SN74LS02D operate at 3.3 V?
No, SN74LS02D is strictly a 5-V TTL device and is not characterized or guaranteed for operation at 3.3 V. Supply voltage must remain within 4.75 V to 5.25 V per its datasheet. Attempting 3.3-V operation results in undefined logic thresholds, excessive propagation delay, and potential output contention. Use 74LVC02 or 74AHC02 for 3.3-V NOR gate applications.
Is SN74LS02D RoHS compliant?
Yes, SN74LS02D is RoHS compliant, with lead finish of Ni/Pd/Au (NIPDAU) and no intentionally added lead. It meets EU Directive 2011/65/EU requirements. Note that earlier variants like JM38510/00401BCA use SnPb (non-RoHS) finishes and are intended for military applications only.
Does SN74LS02D have built-in ESD protection?
SN74LS02D includes basic input clamp diodes to GND and VCC, providing limited ESD immunity per MIL-STD-883 Class 3B (±2 kV HBM). It is not rated for IEC 61000-4-2 contact discharge. For environments with frequent handling or unshielded connectors, external TVS diodes or series resistors are recommended to protect SN74LS02D inputs beyond its intrinsic rating.
What is the difference between SN74LS02D and SN74LS02DR?
SN74LS02D and SN74LS02DR share identical die, electrical specifications, and pinout. The sole difference is packaging: SN74LS02D was offered in tubes (now obsolete), while SN74LS02DR is supplied in tape-and-reel format (2500 pcs) optimized for automated SMT placement. Both operate from 0°C to 70°C and use SOIC-14 (D) package with NIPDAU finish.
SN74LS02D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- NOR Gate
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- 400µA, 16mA
- Input Logic Level - Low:
- 0.8V
- Input Logic Level - High:
- 2V
- Max Propagation Delay @ V, Max CL:
- 15ns @ 5V, 15pF
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LS02D FAQ
1.How can I place an order for SN74LS02D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS02D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS02D reliable?
The price and inventory of SN74LS02D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS02D is usually 5 days.
3.What payment methods are accepted for SN74LS02D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS02D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS02D?
SN74LS02D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS02D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS02D?
For technical support, including SN74LS02D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS02D requirements.
6.How does Aetrix verify that SN74LS02D is sourced from the original manufacturer or authorized distributors?
All SN74LS02D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS02D meets industry standards.
7.What is the process for return or replacement of SN74LS02D?
All SN74LS02D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS02D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS02D part is unused and in its original packaging.
Return procedure for SN74LS02D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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