onsemi SN74LS05D
- Part No.:
- SN74LS05D
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS05D.pdf
- Description:
- IC INVERTER 6CH 1-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:9,400
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Product details
Overview
SN74LS05D from Texas Instruments is a 14-pin SOIC-packaged hex inverter IC with open-collector outputs, designed for logic-level inversion and wired-OR/AND bus interfacing in industrial control and legacy TTL systems. It operates at 4.75–5.25 V, delivers 8 mA sink current per output, exhibits 15–28 ns propagation delay, and supports 0°C to 70°C ambient operation.
For engineers reviewing the SN74LS05D datasheet, pinout, applications, or equivalent options, this page provides verified functional specifications, package dimensions, real-world interface constraints (e.g., mandatory external pull-up resistors), and direct alternatives for legacy system maintenance and board-level replacement.
Technical Context
The SN74LS05D implements six independent open-collector inverters using low-power Schottky (LS) TTL technology. Each inverter features a standard TTL-compatible input threshold (VIL = 0.7 V, VIH = 2.0 V) and requires external pull-up resistors to define VOH and drive bus loads.
Its open-collector architecture enables active-low wired-OR and active-high wired-AND logic functions when multiple outputs share a common pull-up. The device is not internally terminated and does not support push-pull or three-state operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74LS (Low-Power Schottky TTL) - ensures compatibility with legacy 5 V TTL systems while reducing power vs. standard 74xx. |
| Supply Voltage | 4.75–5.25 V - must be regulated within this range; operation outside causes undefined output states or reliability risk. |
| Output Type | Open-collector - requires external pull-up resistor(s); enables wired-logic sharing across multiple devices without contention. |
| Max Sink Current | 8 mA per output - defines minimum pull-up resistance for target VOH (e.g., ≥1 kΩ for 5 V VOH with 4.2 V margin). |
| Propagation Delay | 15–28 ns (tPLH/tPHL) - measured at VCC = 5 V, CL = 15 pF, RL = 2 kΩ; determines maximum clock/data rate in combinational logic paths. |
| Input Thresholds | VIL = 0.7 V, VIH = 2.0 V - compatible with standard TTL and LS logic families; rejects noise below 0.7 V and guarantees switching above 2.0 V. |
| Operating Temperature | 0°C to 70°C - commercial-grade rating; unsuitable for extended automotive or military environments without derating. |
Pinout & Package
SN74LS05D uses a 14-pin SOIC (Small Outline Integrated Circuit) package, 3.9 mm wide, 8.65 mm long, 1.75 mm max height, with 1.27 mm pitch. Pin 1 is marked by a beveled corner or dot.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 5, 9, 11, 13 | Input (1A–6A) | Standard TTL-compatible logic inputs; accept 0–5 V signals; high impedance (IIL = −0.4 mA max). |
| 2, 4, 6, 8, 10, 12 | Output (1Y–6Y) | Open-collector NPN outputs; sink current only; require external pull-up to VCC or higher voltage rail. |
| 7 | GND | Ground reference for all internal circuitry and output sinks; must be low-impedance connection. |
| 14 | VCC | Positive supply (4.75–5.25 V); powers internal logic and defines output high level when pulled up externally. |
Key Features
| Feature | Design Value |
|---|---|
| Hex inverter function | Six independent inverters in one 14-pin SOIC - reduces board space and interconnect count vs. discrete gate solutions. |
| Open-collector outputs | Enables wired-OR logic and level translation - allows interfacing with higher-voltage buses (e.g., 12 V) using appropriate pull-up. |
| Low-power Schottky design | ICCL = 3.6–6.6 mA typical - cuts power vs. standard 7405 (18–33 mA), critical for thermally constrained or battery-backed systems. |
| TTL-compatible thresholds | VIL = 0.7 V, VIH = 2.0 V - ensures interoperability with 74xx, 74LSxx, and microcontroller GPIOs without level shifters. |
| Commercial temperature grade | 0°C to 70°C operation - validated for office, lab, and factory-floor embedded applications with controlled ambient conditions. |
Applications
| Industrial Control Logic | Legacy System Bus Interface |
|---|---|
Use Scenario: Isolating and inverting sensor status signals before feeding into a PLC input module with shared interrupt line. IC Role / Device Role / Timing Role: Open-collector inverter providing level-shifted, noise-immune active-low status indication on a wired-OR interrupt bus. Use Value: Enables multiple sensors to share one interrupt line without hardware OR gates; 8 mA sink capability drives standard PLC input thresholds reliably. |
Use Scenario: Interfacing a modern microcontroller GPIO (3.3 V tolerant) to a legacy 5 V TTL backplane requiring active-low acknowledge pulses. IC Role / Device Role / Timing Role: Level-translating inverter converting 3.3 V logic highs to 5 V-compatible open-collector low pulses. Use Value: Eliminates need for discrete transistor buffers; 15–28 ns delay preserves timing margins in synchronous handshaking protocols. |
| Test Equipment Signal Conditioning | Power Supply Sequencing Monitor |
Use Scenario: Inverting enable signals from a benchtop power supply's digital control IC to drive external relay drivers with inverted polarity. IC Role / Device Role / Timing Role: Signal polarity correction stage ensuring correct activation sequence of downstream power stages. Use Value: Six channels allow simultaneous inversion of multiple supply rails; SOIC package fits dense PCB layouts in compact test fixtures. |
Use Scenario: Monitoring undervoltage lockout (UVLO) outputs from multiple DC/DC converters and combining them into a single system-fail signal. IC Role / Device Role / Timing Role: Wired-AND combiner where any converter fault pulls the shared line low via open-collector outputs. Use Value: No additional logic gates required; inherent OR-to-AND conversion via open-collector topology simplifies fault-tree implementation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS04D | Push-pull (totem-pole) outputs; no external pull-up required; 10 mA IOL; slightly faster (10–15 ns). | Cannot perform wired-OR/AND; unsuitable for bus sharing or level translation; better for point-to-point logic inversion. | Select SN74LS04D when driving CMOS loads or replacing non-bus applications; avoid if wired logic or voltage translation is needed. |
| SN74S05D | Higher speed (2–7 ns), higher power (ICCL = 30–54 mA), 20 mA IOL, same open-collector structure and pinout. | Same bus interface capability but consumes ~8× more supply current; requires tighter thermal management. | Choose SN74S05D only when propagation delay < 7 ns is mandatory; otherwise SN74LS05D offers optimal power/performance balance. |
Compared with SN74LS04D, SN74LS05D enables bus arbitration and level flexibility at lower power; compared with SN74S05D, it reduces thermal load and supply demand while retaining identical interface functionality and pin compatibility.
Availability
SN74LS05D is available at Aetrix Electronics and suitable for industrial control logic, legacy system bus interface, test equipment signal conditioning, and power supply sequencing monitor applications requiring stable component supply and long-term obsolescence mitigation.
Supply support for SN74LS05D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog and embedded processing technologies with broad industrial, automotive, and consumer product portfolios.
The SN74LS05D belongs to TI's legacy 74LS logic family, engineered for reliable, low-power TTL compatibility in retrofitted and maintenance-critical systems where pin-for-pin replacement and long-lifecycle support are essential.
FAQ
What is the required external pull-up resistor value for SN74LS05D outputs?
The SN74LS05D requires an external pull-up resistor on each open-collector output to define VOH. For a 5 V supply and guaranteed VOH ≥ 4.2 V at 8 mA sink, a 100 Ω resistor yields 4.2 V (5 V − 8 mA × 100 Ω); 1 kΩ is typical for general-purpose use. Resistor value must be selected based on load capacitance, speed requirements, and VOH target - lower resistance improves rise time but increases power draw. The SN74LS05D itself does not include internal pull-ups.
Can SN74LS05D drive LEDs directly?
Yes, the SN74LS05D can drive LEDs directly when configured as a low-side switch: connect the LED anode to VCC (5 V) and cathode to an SN74LS05D output pin, with a series current-limiting resistor. With 8 mA max sink current, a 330 Ω resistor limits current to ~12 mA (5 V − 1.8 V LED drop) ÷ 330 Ω ≈ 9.7 mA - within safe operating range. Ensure total output current across all active channels stays within ICCL limits (6.6 mA typical). The SN74LS05D is well-suited for LED status indicators in industrial panels.
Is SN74LS05D pin-compatible with SN7405N or SN74S05D?
Yes, SN74LS05D is pin-compatible with SN7405N (PDIP) and SN74S05D (SOIC) - all share identical 14-pin functional mapping: inputs on pins 1,3,5,9,11,13; outputs on 2,4,6,8,10,12; GND on 7; VCC on 14. However, electrical behavior differs: SN7405N uses standard TTL (higher power, slower), SN74S05D uses Schottky (faster, higher power), while SN74LS05D balances speed and efficiency. The SN74LS05D replaces both in footprint-constrained designs requiring LS characteristics.
Does SN74LS05D support mixed-voltage interfacing, such as 3.3 V inputs?
SN74LS05D accepts 3.3 V logic-high inputs reliably: its VIH threshold is 2.0 V min, and 3.3 V exceeds this by 1.3 V margin. Input current is minimal (IIH = 20 µA max), so 3.3 V MCU GPIOs drive it directly without level shifting. However, outputs remain 5 V-referenced open-collector nodes - to interface with 3.3 V receivers, the pull-up must connect to 3.3 V, not 5 V. The SN74LS05D thus supports mixed-voltage systems when pull-up voltage is matched to the receiving logic family.
What is the maximum capacitive load SN74LS05D can drive while maintaining specified propagation delay?
The SN74LS05D's specified propagation delay (15–28 ns) is characterized at CL = 15 pF and RL = 2 kΩ. Driving loads >15 pF increases rise time nonlinearly: at CL = 50 pF, tPLH/tPHL degrades to ~32 ns (per SN74S05 data, used as upper-bound proxy). For reliable timing, keep total load (trace + receiver + probe capacitance) ≤15 pF. If higher capacitance is unavoidable, reduce RL (e.g., 470 Ω) to maintain edge speed - but verify that resulting sink current (e.g., 5 V ÷ 470 Ω ≈ 10.6 mA) remains within the SN74LS05D's 8 mA absolute max rating per output.
SN74LS05D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 6
- Number of Inputs:
- 1
- Features:
- Open Collector
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Quiescent (Max):
- -
- Current - Output High, Low:
- -, 8mA
- Input Logic Level - Low:
- 0.8V
- Input Logic Level - High:
- 2V
- Max Propagation Delay @ V, Max CL:
- 32ns @ 5V, 15pF
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LS05D FAQ
1.How can I place an order for SN74LS05D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS05D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS05D reliable?
The price and inventory of SN74LS05D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS05D is usually 5 days.
3.What payment methods are accepted for SN74LS05D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS05D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS05D?
SN74LS05D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS05D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS05D?
For technical support, including SN74LS05D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS05D requirements.
6.How does Aetrix verify that SN74LS05D is sourced from the original manufacturer or authorized distributors?
All SN74LS05D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS05D meets industry standards.
7.What is the process for return or replacement of SN74LS05D?
All SN74LS05D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS05D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS05D part is unused and in its original packaging.
Return procedure for SN74LS05D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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