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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments SN74LS109AD

Name: SN74LS109AD
Brand: Texas Instruments
SKU: SN74LS109AD
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS109AD

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74LS109AD.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SOIC

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Product details

Overview

SN74LS109AD from Texas Instruments is a dual positive-edge-triggered J-K flip-flop with individual set and reset inputs, 16-pin SOIC package, 0°C to 70°C operating temperature, and TTL-compatible logic levels. It serves as a synchronous storage element in digital control sequencers and state machines.

For engineers reviewing the SN74LS109AD datasheet, SN74LS109AD pinout, SN74LS109AD application, or SN74LS109AD equivalent, key selection criteria include edge-triggering behavior, independent asynchronous controls per section, propagation delay (typically 15 ns), power supply tolerance (4.75 V to 5.25 V), and compatibility with legacy LS-TTL system designs.

Technical Context

The SN74LS109AD implements two independent J-K flip-flops, each with separate J, K, clock, set (SD), and reset (RD) terminals. Each section operates on the rising edge of the clock signal and supports asynchronous active-low set and reset functions.

It uses bipolar transistor–transistor logic (TTL) architecture with Schottky-clamped outputs, delivering guaranteed fan-out of 20 LS-TTL loads and typical output drive capability of –0.4 mA (high) / 8 mA (low) at V_CC = 5 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	LS-TTL - ensures interoperability with legacy 74LS-series systems and predictable noise margins.
Function	Dual J-K flip-flop with independent SD/RD - enables discrete control of each latch without shared reset paths.
Trigger Edge	Positive-edge clock - synchronizes state changes precisely at rising transitions, critical for deterministic timing.
t_PLH/t_PHL	15 ns max (V_CC = 5 V, T_A = 25°C) - defines maximum clock-to-Q delay for timing budgeting in sequential logic.
V_CC Range	4.75 V to 5.25 V - mandates regulated 5 V supply; no operation outside this narrow window.
I_OH/I_OL	–0.4 mA / 8 mA - specifies output current capability for driving downstream LS-TTL inputs or small LEDs directly.
Operating Temperature	0°C to 70°C - qualifies for commercial-grade applications only; not rated for industrial or extended ranges.

Pinout & Package

SN74LS109AD is housed in a 16-pin SOIC (Small Outline Integrated Circuit) package, 3.9 mm body width, with standard JEDEC MO-001AC footprint and gull-wing leads.

Pin/Terminal	Circuit Role	Design Meaning
1, 15	J input (Section A/B)	Data enable for set action on next clock edge; high = prepare for toggle/set, low = prepare for reset/clear.
2, 14	K input (Section A/B)	Data enable for reset action on next clock edge; high = prepare for toggle/reset, low = prepare for set.
3, 13	CLK (Section A/B)	Positive-edge-triggered clock input; state change occurs only at rising transition.
4, 12	SD (Section A/B)	Asynchronous active-low set - forces Q = 1 regardless of clock or J/K state.
5, 11	RD (Section A/B)	Asynchronous active-low reset - forces Q = 0 regardless of clock or J/K state.
6, 10	Q (Section A/B)	True output - reflects stored logic state after clock edge or asynchronous control activation.
7, 9	Q̅ (Section A/B)	Complementary output - provides inverted state for feedback or differential signaling.
8	GND	Power ground reference - must be low-impedance connection to minimize switching noise coupling.
16	V_CC	+5 V supply - requires local 0.1 µF ceramic decoupling capacitor placed within 5 mm of pin.

Key Features

Feature	Design Value
Independent Set/Reset per Section	Enables asymmetric initialization of two latches-e.g., one section preset while the other cleared-without external gating logic.
Rising-Edge Clock Sensitivity	Eliminates metastability risk from asynchronous sampling; supports clean synchronization of external signals into synchronous domains.
LS-TTL Compatible Input Thresholds	V_IL ≤ 0.8 V, V_IH ≥ 2.0 V - ensures reliable interfacing with 74LS, 74ALS, and microcontroller GPIOs operating at 5 V.
Guaranteed Fan-Out of 20	Supports direct drive of up to 20 LS-TTL inputs without buffer amplification-reducing component count in dense logic arrays.
SOIC Packaging	Surface-mount 16-pin SOIC (D) package with 1.27 mm pitch-enables automated assembly and higher board density than through-hole alternatives.

Applications

Industrial Control Sequencing	Digital Test Equipment Counters
Use Scenario: Implementing step-indexed machine motion control where each J-K stage advances a motor phase sequence based on encoder pulses. IC Role / Device Role / Timing Role: Synchronous state register holding current step position; clocked by encoder index pulse, with SD/RD used for homing or emergency stop. Use Value: Independent SD/RD allows immediate repositioning to known states without waiting for clock edges-critical for safety-critical axis recovery.	Use Scenario: Building a 4-bit binary counter in automated test fixtures that measures frequency of unknown signals using gate-time-controlled accumulation. IC Role / Device Role / Timing Role: Cascaded J-K flip-flop forming modulo-16 counter; clocked by divided-down reference oscillator with synchronous load via SD/RD. Use Value: Positive-edge triggering ensures precise alignment with system timing reference-minimizing counting ambiguity during high-speed signal capture.
Legacy System Logic Replacement	LED Display Multiplexing Controller
Use Scenario: Replacing obsolete 74LS76A in field-upgraded avionics display controllers where form-factor and pinout match are mandatory. IC Role / Device Role / Timing Role: Drop-in functional replacement for dual J-K function; retains identical SOIC-16 footprint and electrical interface. Use Value: Maintains full backward compatibility with existing PCB layout and firmware-eliminating redesign cost and qualification delays.	Use Scenario: Driving 8-segment LED digits in embedded instrumentation panels using time-multiplexed column selection and row data latching. IC Role / Device Role / Timing Role: Dual latch storing digit segment patterns; clocked by multiplex scan signal, with SD/RD enabling blanking between frames. Use Value: Asynchronous reset ensures flicker-free blanking-no visible ghosting during digit transitions due to guaranteed Q=0 hold during reinitialization.

Industrial Control Sequencing

Digital Test Equipment Counters

Use Scenario: Implementing step-indexed machine motion control where each J-K stage advances a motor phase sequence based on encoder pulses.

IC Role / Device Role / Timing Role: Synchronous state register holding current step position; clocked by encoder index pulse, with SD/RD used for homing or emergency stop.

Use Value: Independent SD/RD allows immediate repositioning to known states without waiting for clock edges-critical for safety-critical axis recovery.

Use Scenario: Building a 4-bit binary counter in automated test fixtures that measures frequency of unknown signals using gate-time-controlled accumulation.

IC Role / Device Role / Timing Role: Cascaded J-K flip-flop forming modulo-16 counter; clocked by divided-down reference oscillator with synchronous load via SD/RD.

Use Value: Positive-edge triggering ensures precise alignment with system timing reference-minimizing counting ambiguity during high-speed signal capture.

Legacy System Logic Replacement

LED Display Multiplexing Controller

Use Scenario: Replacing obsolete 74LS76A in field-upgraded avionics display controllers where form-factor and pinout match are mandatory.

IC Role / Device Role / Timing Role: Drop-in functional replacement for dual J-K function; retains identical SOIC-16 footprint and electrical interface.

Use Value: Maintains full backward compatibility with existing PCB layout and firmware-eliminating redesign cost and qualification delays.

Use Scenario: Driving 8-segment LED digits in embedded instrumentation panels using time-multiplexed column selection and row data latching.

IC Role / Device Role / Timing Role: Dual latch storing digit segment patterns; clocked by multiplex scan signal, with SD/RD enabling blanking between frames.

Use Value: Asynchronous reset ensures flicker-free blanking-no visible ghosting during digit transitions due to guaranteed Q=0 hold during reinitialization.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS76AN	Master-slave J-K flip-flop with complementary outputs; negative-edge triggered; PDIP-16 only.	Lacks independent SD/RD per section; uses common reset/set; unsuitable for asymmetric initialization.	Select when master-slave architecture is required for reduced race conditions in cascaded counters.
SN74LS112ADR	Same dual J-K function but with negative-edge clock; SOIC-16; identical SD/RD structure and timing specs.	Requires inverted clock signal or logic inversion; otherwise pin- and functionally compatible in most designs.	Choose when system clock polarity aligns with falling-edge sampling or when replacing SN74LS112A variants.

Compared with SN74LS76AN and SN74LS112ADR, the SN74LS109AD uniquely offers positive-edge triggering with fully independent asynchronous controls-making it optimal for applications requiring precise rising-edge synchronization and per-section state override without additional logic.

Availability

SN74LS109AD is available at Aetrix Electronics and suitable for industrial control sequencers, digital test equipment counters, and legacy system logic replacement requiring stable component supply and long-term obsolescence mitigation support.

Supply support for SN74LS109AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs for industrial, automotive, and communications markets.

The SN74LS109AD belongs to TI's legacy 74LS logic family, designed specifically for robust, low-power TTL-compatible digital control in commercial-grade systems where reliability and interoperability with established designs are essential.

FAQ

Is SN74LS109AD still in active production?

No, SN74LS109AD is marked as Obsolete in TI's official packaging documentation. However, Aetrix Electronics maintains limited legacy inventory and offers traceable, tested units for repair and continuity programs. The active variant SN74LS109ADR remains available in SOIC packaging with RoHS compliance and tape-and-reel delivery.

What is the maximum clock frequency supported by SN74LS109AD?

The SN74LS109AD does not specify a maximum clock frequency in its datasheet; instead, timing is governed by minimum pulse width requirements. The shortest valid clock high/low time is 20 ns each, implying a theoretical upper limit near 25 MHz under ideal conditions-but practical use is typically ≤10 MHz due to propagation delay accumulation and setup/hold constraints.

Can SN74LS109AD drive LEDs directly without current-limiting resistors?

No. Although SN74LS109AD can sink up to 8 mA per output, direct LED connection without series resistance risks exceeding absolute maximum ratings and causing premature failure. A minimum 330 Ω resistor is required for standard 2 V red LEDs at 5 V supply to limit current to ~9 mA-within safe I_OL limits but respecting thermal derating.

Does SN74LS109AD support mixed-voltage interfacing with 3.3 V logic?

No. SN74LS109AD is strictly a 5 V-only device with TTL input thresholds (V_IH ≥ 2.0 V, V_IL ≤ 0.8 V). While 3.3 V CMOS outputs may meet V_IH, they often fail to guarantee V_IL margin under noise or loading. Level-shifting or buffer ICs are required for reliable interoperation with 3.3 V systems.

How does the asynchronous reset behavior of SN74LS109AD interact with the clock signal?

The asynchronous reset (RD) and set (SD) inputs of SN74LS109AD take immediate effect regardless of clock state-overriding all J, K, and CLK activity. When RD is pulled low, Q goes low and Q̅ goes high within t_PHL (max 15 ns); the clock is ignored until RD returns high. This allows deterministic state clearing without waiting for clock edges.

SN74LS109AD Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 33 MHz

Max Propagation Delay @ V, Max CL:: 40ns @ 5V, 15pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 400µA, 8mA

Voltage - Supply:: 4.75V ~ 5.25V

Current - Quiescent (Iq):: 8 mA

Input Capacitance:: -

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74LS109AD FAQ

1.How can I place an order for SN74LS109AD through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS109AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS109AD reliable?

The price and inventory of SN74LS109AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS109AD is usually 5 days.

3.What payment methods are accepted for SN74LS109AD?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS109AD transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS109AD?

SN74LS109AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS109AD order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS109AD?

For technical support, including SN74LS109AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS109AD requirements.

6.How does Aetrix verify that SN74LS109AD is sourced from the original manufacturer or authorized distributors?

All SN74LS109AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS109AD meets industry standards.

7.What is the process for return or replacement of SN74LS109AD?

All SN74LS109AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS109AD, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS109AD part is unused and in its original packaging.

Return procedure for SN74LS109AD:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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