Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments SN74LS109ANG4

Name: SN74LS109ANG4
Brand: Texas Instruments
SKU: SN74LS109ANG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN74LS109ANG4

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: SN74LS109ANG4.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16DIP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,130

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN74LS109ANG4 from Texas Instruments is a dual positive-edge-triggered JK flip-flop with individual J, K, clock, set, and reset inputs per section, operating at 0°C to 70°C, with typical propagation delay of 25 ns (t_PLH/t_PHL), V_CC = 5 V, and TTL-compatible input thresholds. It serves as a synchronous state-storage element in digital control logic, serial data synchronization, and counter design.

For engineers reviewing the SN74LS109ANG4 datasheet, SN74LS109ANG4 pinout, SN74LS109ANG4 application, or SN74LS109ANG4 equivalent, key selection considerations include its dual independent JK functionality, edge-triggered operation, complementary Q/Q̅ outputs, and PDIP-16 packaging for through-hole prototyping and legacy industrial control systems.

Technical Context

The SN74LS109ANG4 implements two identical, independently controlled JK flip-flops in a single 16-pin plastic DIP package. Each section features separate asynchronous active-low preset (PR̅) and clear (CLR̅) inputs, synchronous positive-edge-triggered clock (CLK), and standard J/K data inputs.

It operates strictly within the TTL logic family voltage and timing constraints: V_CC = 4.75–5.25 V, input high threshold ≈ 2.0 V, input low threshold ≈ 0.8 V, and guaranteed fan-out of 20 LS-TTL loads. No internal pull-ups, level-shifting, or CMOS compatibility is provided.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	LS-TTL - ensures interoperability with 74LS-series components and defined noise margins at 5 V.
Function	Dual JK flip-flop - provides two independent, edge-triggered bistable storage elements in one IC.
Trigger Edge	Positive clock edge - state changes occur only on rising CLK transitions, enabling synchronous system timing.
t_PD (max)	40 ns at V_CC = 5 V, T_A = 25°C - defines worst-case delay from CLK edge to output valid, critical for setup/hold timing closure.
Supply Voltage	4.75 V to 5.25 V - narrow tolerance requires stable 5 V rail; operation outside this range may cause metastability or failure.
Operating Temperature	0°C to 70°C - commercial-grade rating; not suitable for extended industrial (-40°C to 85°C) or military (-55°C to 125°C) environments.
Output Type	Complementary Q and Q̅ - enables direct connection to downstream logic without external inverters for toggle or feedback paths.

Pinout & Package

SN74LS109ANG4 is housed in a 16-pin plastic dual in-line package (PDIP-N), 0.300-inch wide body, with standard through-hole mounting and 0.100-inch pin pitch. Pin 1 is located at the top-left corner adjacent to the notch or dot marking.

Pin/Terminal	Circuit Role	Design Meaning
1	1PR̅	Active-low asynchronous preset for Flip-Flop 1 - forces Q1 = 1, Q̅1 = 0 regardless of clock or J/K state.
2	1J	Data input J for Flip-Flop 1 - controls set behavior on next positive clock edge when K = 0.
3	1CLK	Positive-edge-triggered clock for Flip-Flop 1 - samples J/K inputs only at rising transition.
4	1K	Data input K for Flip-Flop 1 - controls reset behavior on next positive clock edge when J = 0.
5	1CLR̅	Active-low asynchronous clear for Flip-Flop 1 - forces Q1 = 0, Q̅1 = 1 regardless of clock or J/K state.
6	1Q̅	Inverted output of Flip-Flop 1 - complements Q1; used for feedback, toggle mode, or differential signaling.
7	GND	Ground reference - must be connected to system 0 V plane; decoupling capacitor recommended near pin.
8	2Q̅	Inverted output of Flip-Flop 2 - electrically isolated from Q1 path; supports independent dual-channel operation.
9	2CLR̅	Active-low asynchronous clear for Flip-Flop 2 - independent control; no coupling to Flip-Flop 1.
10	2K	Data input K for Flip-Flop 2 - functionally identical to Pin 4 but for second section.
11	2CLK	Positive-edge-triggered clock for Flip-Flop 2 - separate timing domain; allows staggered or independent triggering.
12	2J	Data input J for Flip-Flop 2 - fully independent of Pin 2; enables dual asynchronous data paths.
13	2PR̅	Active-low asynchronous preset for Flip-Flop 2 - independent of Pin 1; supports dual initialization.
14	V_CC	+5 V power supply - must be filtered and regulated; typical current draw ≤ 30 mA at full toggle rate.
15	1Q	True output of Flip-Flop 1 - primary state output; drives standard LS-TTL fan-out (20 loads).
16	2Q	True output of Flip-Flop 2 - matches Pin 15 electrical characteristics; supports parallel or cascaded use.

Key Features

Feature	Design Value
Dual independent JK sections	Enables two separate synchronous state machines in one package - reduces board space and interconnect complexity vs. discrete flip-flops.
Asynchronous preset and clear	Allows immediate initialization or forced reset without waiting for clock edge - essential for power-on reset and fault recovery circuits.
Complementary Q/Q̅ outputs	Eliminates need for external inverters in toggle, shift-register, or feedback configurations - improves timing predictability and signal integrity.
Positive-edge clocking	Synchronizes state updates to rising CLK edges only - prevents unintended toggling from noise or slow-rising clocks.
TTL-compatible input thresholds	Guarantees reliable recognition of 0.8 V (V_IL) and 2.0 V (V_IH) logic levels - ensures interoperability across 74LS, 74S, and 74F families.

Applications

Industrial Control Sequencing	Serial-to-Parallel Data Conversion
Use Scenario: A programmable logic controller (PLC) uses discrete timing steps to sequence motor start/stop, valve actuation, and sensor sampling in fixed-order cycles. IC Role / Device Role / Timing Role: SN74LS109ANG4 acts as a synchronous step register - each flip-flop holds one bit of the current step index, updated on master clock edges. Use Value: Dual JK structure allows compact 2-bit state encoding with independent preset/clear for emergency stop or cycle restart without software intervention.	Use Scenario: A microcontroller transmits serial status data (e.g., sensor alarms) to an LED display panel requiring parallel 4-bit input. IC Role / Device Role / Timing Role: SN74LS109ANG4 functions as a 2-bit stage in a 4-bit shift register - cascaded with another SN74LS109ANG4 to capture and hold incoming bits. Use Value: Complementary outputs simplify feedback wiring for serial-in/parallel-out (SIPO) operation; edge-triggered clock ensures clean bit alignment.
Binary Counter Building Block	Glitch-Free Toggle Circuit
Use Scenario: A test instrument requires a stable 4-bit binary counter driven by a 1 MHz clock for frequency division and event counting. IC Role / Device Role / Timing Role: SN74LS109ANG4 serves as a toggle-capable flip-flop stage - J=K=1 configuration enables divide-by-2 operation per section. Use Value: Guaranteed 40 ns max propagation delay ensures setup time margin for cascaded counters up to 10 MHz input clock frequency.	Use Scenario: A power management circuit needs a hardware-based toggle switch for enable/disable control, immune to mechanical switch bounce. IC Role / Device Role / Timing Role: SN74LS109ANG4 operates in toggle mode (J=K=1) with debounced push-button feeding CLK, while PR̅/CLR̅ hold initial state. Use Value: Asynchronous preset/clear allows deterministic startup state (e.g., "off"); positive-edge triggering rejects contact chatter below 40 ns duration.

Industrial Control Sequencing

Serial-to-Parallel Data Conversion

Use Scenario: A programmable logic controller (PLC) uses discrete timing steps to sequence motor start/stop, valve actuation, and sensor sampling in fixed-order cycles.

IC Role / Device Role / Timing Role: SN74LS109ANG4 acts as a synchronous step register - each flip-flop holds one bit of the current step index, updated on master clock edges.

Use Value: Dual JK structure allows compact 2-bit state encoding with independent preset/clear for emergency stop or cycle restart without software intervention.

Use Scenario: A microcontroller transmits serial status data (e.g., sensor alarms) to an LED display panel requiring parallel 4-bit input.

IC Role / Device Role / Timing Role: SN74LS109ANG4 functions as a 2-bit stage in a 4-bit shift register - cascaded with another SN74LS109ANG4 to capture and hold incoming bits.

Use Value: Complementary outputs simplify feedback wiring for serial-in/parallel-out (SIPO) operation; edge-triggered clock ensures clean bit alignment.

Binary Counter Building Block

Glitch-Free Toggle Circuit

Use Scenario: A test instrument requires a stable 4-bit binary counter driven by a 1 MHz clock for frequency division and event counting.

IC Role / Device Role / Timing Role: SN74LS109ANG4 serves as a toggle-capable flip-flop stage - J=K=1 configuration enables divide-by-2 operation per section.

Use Value: Guaranteed 40 ns max propagation delay ensures setup time margin for cascaded counters up to 10 MHz input clock frequency.

Use Scenario: A power management circuit needs a hardware-based toggle switch for enable/disable control, immune to mechanical switch bounce.

IC Role / Device Role / Timing Role: SN74LS109ANG4 operates in toggle mode (J=K=1) with debounced push-button feeding CLK, while PR̅/CLR̅ hold initial state.

Use Value: Asynchronous preset/clear allows deterministic startup state (e.g., "off"); positive-edge triggering rejects contact chatter below 40 ns duration.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual JK flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS76AN	Dual JK flip-flop with active-low clock enable (CLKEN̅); no individual J/K pins per section - J and K tied internally to V_CC or GND for toggle/set/reset modes.	Limited to fixed-function modes (toggle, set, reset); cannot implement arbitrary synchronous logic like gated J/K transitions.	Select SN74LS76AN only if application requires simple toggle or preset/reset without dynamic J/K control per clock cycle.
SN74LS112AN	Dual JK flip-flop with negative-edge triggering (CLK inverted internally); otherwise identical pinout and DC specs to SN74LS109ANG4.	Requires inverted clock signal or redesign of timing source; incompatible with positive-edge-synchronized systems without buffer inversion.	Choose SN74LS112AN only when system clock architecture is inherently negative-edge referenced or when inverting the clock is acceptable.

Compared with SN74LS76AN and SN74LS112AN, the SN74LS109ANG4 uniquely supports full synchronous J/K data control on each positive clock edge, making it the only option among the three for implementing arbitrary next-state logic in sequential circuits without external gating.

Availability

SN74LS109ANG4 is available at Aetrix Electronics and suitable for industrial control sequencing, serial-to-parallel data conversion, binary counter building, and glitch-free toggle circuits requiring stable component supply and long-term obsolescence support.

Supply support for SN74LS109ANG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and communications portfolio coverage.

The SN74LS109ANG4 belongs to TI's legacy 74LS logic family, designed specifically for robust, low-power TTL-compatible digital control in commercial-temperature industrial and instrumentation applications.

FAQ

What is the maximum clock frequency supported by the SN74LS109ANG4?

The SN74LS109ANG4 does not specify a maximum clock frequency in its datasheet; instead, timing is governed by minimum pulse width and setup/hold requirements. With t_PLH/t_PHL ≤ 40 ns and t_W (clock pulse width) ≥ 20 ns, reliable operation is achievable up to approximately 10 MHz in well-designed layouts. The SN74LS109ANG4 must meet all AC timing specifications including t_su (J/K setup) = 20 ns and t_h (J/K hold) = 5 ns relative to CLK edge.

Does the SN74LS109ANG4 support asynchronous operation?

Yes, the SN74LS109ANG4 supports full asynchronous control via active-low preset (PR̅) and clear (CLR̅) inputs on both flip-flop sections. These inputs override clock and J/K states immediately - asserting PR̅ forces Q = 1, Q̅ = 0; asserting CLR̅ forces Q = 0, Q̅ = 1. The SN74LS109ANG4 maintains these states until the respective input is de-asserted, independent of clock activity.

Can the SN74LS109ANG4 be used in place of the SN74LS76AN?

No - the SN74LS109ANG4 is not a drop-in replacement for the SN74LS76AN. While both are dual JK flip-flops in PDIP-16 packages, the SN74LS76AN lacks individual J and K inputs per section and instead offers clock enable (CLKEN̅) and fixed-mode control. Their pinouts differ: SN74LS76AN assigns Pins 3/4 to CLKEN̅/CLK, not J/K. Direct substitution would require PCB redesign and logic reimplementation.

What is the meaning of "NG4" in SN74LS109ANG4?

The "NG4" suffix in SN74LS109ANG4 indicates a specific assembly and test variant within Texas Instruments' packaging nomenclature. It denotes the PDIP-16 package with NiPdAu (NIPDAU) lead finish, RoHS-compliant, and tube packaging (25 units per tube). This suffix distinguishes it from other variants like SN74LS109ADR (SOIC, tape-and-reel) or SN74LS109ANSR (SOP). The SN74LS109ANG4 remains functionally identical to SN74LS109AN across all electrical and timing specifications.

Is the SN74LS109ANG4 compatible with 3.3 V logic systems?

No, the SN74LS109ANG4 is not compatible with 3.3 V logic systems. It is a strict 5 V TTL device requiring V_CC = 4.75–5.25 V and exhibiting TTL input thresholds (V_IH ≈ 2.0 V, V_IL ≈ 0.8 V). Driving its inputs from 3.3 V logic may result in marginal or undefined switching, and its outputs swing near 0 V / 3.5 V - insufficient to reliably drive standard TTL or LVTTL inputs. Level-shifting circuitry is required for interfacing with 3.3 V systems.

SN74LS109ANG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Tube

Product Status:: Discontinued at Digi-Key

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 33 MHz

Max Propagation Delay @ V, Max CL:: 25ns @ 5V, 15pF

Trigger Type:: Positive Edge

Current - Output High, Low:: 400µA, 8mA

Voltage - Supply:: 4.75V ~ 5.25V

Current - Quiescent (Iq):: 8 mA

Input Capacitance:: -

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-PDIP

SN74LS109ANG4 FAQ

1.How can I place an order for SN74LS109ANG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS109ANG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS109ANG4 reliable?

The price and inventory of SN74LS109ANG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS109ANG4 is usually 5 days.

3.What payment methods are accepted for SN74LS109ANG4?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS109ANG4 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS109ANG4?

SN74LS109ANG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS109ANG4 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS109ANG4?

For technical support, including SN74LS109ANG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS109ANG4 requirements.

6.How does Aetrix verify that SN74LS109ANG4 is sourced from the original manufacturer or authorized distributors?

All SN74LS109ANG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS109ANG4 meets industry standards.

7.What is the process for return or replacement of SN74LS109ANG4?

All SN74LS109ANG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS109ANG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS109ANG4 part is unused and in its original packaging.

Return procedure for SN74LS109ANG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…