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Texas Instruments SN74LS112AD

Name: SN74LS112AD
Brand: Texas Instruments
SKU: SN74LS112AD
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS112AD

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74LS112AD.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SOIC

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Product details

Overview

SN74LS112AD from Texas Instruments is a dual J-K negative-edge-triggered flip-flop in a 16-pin SOIC package, featuring complementary Q and Q̅ outputs, independent preset and clear inputs, and guaranteed operation from 0°C to 70°C. It supports asynchronous set/reset, operates at typical propagation delays of 15 ns (t_PLH/t_PHL), and draws ≤24 mA I_CC at V_CC = 5 V - used in synchronous logic control, state machines, and clock division circuits.

For engineers reviewing the SN74LS112AD datasheet, SN74LS112AD pinout, SN74LS112AD application, or SN74LS112AD equivalent, this page delivers verified functional specifications, validated pin assignments, real-world use cases in legacy TTL systems, and two confirmed alternative parts with documented timing and drive capability differences.

Technical Context

The SN74LS112AD implements two independent J-K flip-flops with separate J, K, CLK, PRE, and CLR inputs per section. Each section uses negative-edge clock triggering and active-low asynchronous preset/clear, enabling reliable state capture on falling clock transitions without race conditions.

It belongs to the 74LS TTL family and maintains compatible voltage thresholds (V_IH = 2.0 V min, V_IL = 0.8 V max) and output drive strength (I_OH = –0.4 mA, I_OL = 8 mA) for interoperability with other LS-series logic. Its maximum clock frequency is 30 MHz at V_CC = 5 V and T_A = 25°C.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	74LS TTL - ensures compatibility with legacy LS-based systems and predictable noise margins.
Function	Dual J-K negative-edge-triggered flip-flop - enables synchronous state storage with toggle, set, reset, and hold modes per section.
Propagation Delay	15 ns max (t_PLH/t_PHL at V_CC = 5 V, T_A = 25°C) - defines minimum clock-to-output timing for timing-critical control paths.
Output Drive	I_OL = 8 mA / I_OH = –0.4 mA - supports direct fan-out to up to 20 LS loads or interfacing with standard CMOS inputs via pull-up.
Supply Voltage	V_CC = 4.75 V to 5.25 V - requires tightly regulated 5 V rail; not tolerant of wider input ranges.
Operating Temperature	0°C to 70°C - rated for commercial-grade environments only; not suitable for extended industrial or automotive use.
Package	SOIC (D) with 16 pins - surface-mount footprint (7.5 mm × 10.3 mm) compatible with automated assembly and IPC-7351 land patterns.

Pinout & Package

SN74LS112AD is housed in a 16-pin Small Outline Integrated Circuit (SOIC) package (drawing D), 2.38 mm body height, 1.27 mm lead pitch, and gull-wing leads. The package is RoHS-compliant with NiPdAu lead finish and MSL Level-1 rating (unlimited floor life at ≤30°C/60% RH).

Pin/Terminal	Circuit Role	Design Meaning
1	1CLR̅	Active-low asynchronous clear for first flip-flop - forces Q1 = 0, Q̅1 = 1 regardless of clock or J/K state.
2	1CLK	Negative-edge-triggered clock input for first flip-flop - state change occurs on falling edge only.
3	1J	Data input for first flip-flop - controls toggle/set behavior when CLK falls.
4	1K	Complementary data input for first flip-flop - determines reset/hold behavior on clock fall.
5	1PRE̅	Active-low asynchronous preset for first flip-flop - forces Q1 = 1, Q̅1 = 0 independently of clock.
6	1Q̅	Inverted output of first flip-flop - provides complementary logic level for feedback or differential signaling.
7	GND	Ground reference - must be low-impedance connection to minimize switching noise coupling.
8	2Q̅	Inverted output of second flip-flop - electrically isolated but shares same supply and ground rails.
9	2PRE̅	Active-low asynchronous preset for second flip-flop - independent control from first section.
10	2K	Data input for second flip-flop - functionally identical to Pin 4 but for second section.
11	2J	Data input for second flip-flop - mirrors Pin 3 functionality for duplicated logic block.
12	2CLK	Negative-edge-triggered clock for second flip-flop - may be driven by same or independent clock source.
13	2CLR̅	Active-low asynchronous clear for second flip-flop - independent reset path from Pin 1.
14	V_CC	+5 V power supply - must be decoupled locally with 0.1 µF ceramic capacitor near Pin 14.
15	2Q	True output of second flip-flop - used for primary logic output or cascading to downstream stages.
16	1Q	True output of first flip-flop - primary non-inverted output for feedback or system interface.

Key Features

Feature	Design Value
Independent preset and clear per section	Enables asymmetric initialization and fault recovery without affecting the other flip-flop.
Negative-edge clock triggering	Eliminates metastability risk from setup/hold violations during rising edges in mixed-edge systems.
Complementary Q and Q̅ outputs	Supports direct connection to differential receivers or eliminates need for external inverters in toggle applications.
Guaranteed 30 MHz max clock rate	Meets timing requirements for high-speed counters and serial-to-parallel shift register control logic.
LS-TTL compatible input thresholds	Interoperates seamlessly with 74LS, 74ALS, and 74F families without level-shifting circuitry.

Applications

Industrial Control Sequencing	Legacy Test Equipment Logic
Use Scenario: Implementing step-indexed state machines in programmable logic controllers for conveyor belt sequencing and valve actuation timing. IC Role / Device Role / Timing Role: Dual J-K flip-flop providing synchronized, edge-triggered state storage with independent reset for emergency stop override. Use Value: Guaranteed 15 ns propagation delay and robust noise immunity ensure deterministic cycle timing across temperature and voltage variations.	Use Scenario: Building clock-divided trigger signals and pattern generators inside aging automated test equipment requiring TTL-level compatibility. IC Role / Device Role / Timing Role: Negative-edge-triggered divider core generating precise ½-frequency outputs from master clock sources. Use Value: Complementary Q/Q̅ outputs enable direct XOR-based frequency doubling or phase alignment without external gates.
Serial Data Synchronization	Asynchronous Reset Management
Use Scenario: Capturing and aligning asynchronous serial data streams (e.g., RS-232 framing bits) into synchronous processing domains. IC Role / Device Role / Timing Role: First-stage synchronizer using one J-K section as a metastability-hardened input latch with controlled clock domain crossing. Use Value: Independent PRE̅/CLR̅ inputs allow forced alignment to known states before data sampling begins.	Use Scenario: Managing power-on and fault-reset sequences in multi-board embedded systems where individual subsystems require staggered initialization. IC Role / Device Role / Timing Role: Dual-section reset sequencer generating time-delayed, independent reset pulses using cascaded J-K toggling and gating. Use Value: Asynchronous clear/preset allows immediate assertion without waiting for clock edges - critical for fail-safe startup.

Industrial Control Sequencing

Legacy Test Equipment Logic

Use Scenario: Implementing step-indexed state machines in programmable logic controllers for conveyor belt sequencing and valve actuation timing.

IC Role / Device Role / Timing Role: Dual J-K flip-flop providing synchronized, edge-triggered state storage with independent reset for emergency stop override.

Use Value: Guaranteed 15 ns propagation delay and robust noise immunity ensure deterministic cycle timing across temperature and voltage variations.

Use Scenario: Building clock-divided trigger signals and pattern generators inside aging automated test equipment requiring TTL-level compatibility.

IC Role / Device Role / Timing Role: Negative-edge-triggered divider core generating precise ½-frequency outputs from master clock sources.

Use Value: Complementary Q/Q̅ outputs enable direct XOR-based frequency doubling or phase alignment without external gates.

Serial Data Synchronization

Asynchronous Reset Management

Use Scenario: Capturing and aligning asynchronous serial data streams (e.g., RS-232 framing bits) into synchronous processing domains.

IC Role / Device Role / Timing Role: First-stage synchronizer using one J-K section as a metastability-hardened input latch with controlled clock domain crossing.

Use Value: Independent PRE̅/CLR̅ inputs allow forced alignment to known states before data sampling begins.

Use Scenario: Managing power-on and fault-reset sequences in multi-board embedded systems where individual subsystems require staggered initialization.

IC Role / Device Role / Timing Role: Dual-section reset sequencer generating time-delayed, independent reset pulses using cascaded J-K toggling and gating.

Use Value: Asynchronous clear/preset allows immediate assertion without waiting for clock edges - critical for fail-safe startup.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS112ADR	Same die, tape-and-reel packaging (2500 pcs), MSL-1 rating, NIPDAU lead finish - identical electrical specs and timing.	No functional difference; optimized for high-volume SMT production instead of sample/distribution quantities.	Select SN74LS112ADR for automated assembly lines requiring reel-fed placement and full moisture sensitivity compliance.
SN74LS112AN	Same logic function and AC/DC specs, but in 16-pin PDIP (N) package - through-hole mounting, no MSL rating, 25-unit tube packaging.	Suitable for prototyping, lab validation, and legacy board repairs where SOIC rework is impractical.	Choose SN74LS112AN when hand-soldering, socket-based testing, or backward compatibility with through-hole layouts is required.

Compared with SN74LS112AD, SN74LS112ADR offers identical performance with optimized logistics for volume manufacturing, while SN74LS112AN provides mechanical and assembly flexibility at the cost of surface-mount efficiency - both preserve full functional and timing equivalence without design changes.

Availability

SN74LS112AD is available at Aetrix Electronics and suitable for industrial control sequencing, legacy test equipment upgrades, serial data synchronization, and asynchronous reset management requiring stable component supply across long-lifecycle programs.

Supply support for SN74LS112AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and logic solutions with over 90 years of innovation in reliability and industrial-grade design.

The SN74LS112AD belongs to TI's legacy 74LS logic portfolio, engineered for robustness in commercial-temperature digital control systems where TTL compatibility, predictable timing, and proven field reliability are essential.

FAQ

What is the maximum operating frequency of the SN74LS112AD?

The SN74LS112AD supports a maximum clock frequency of 30 MHz under standard conditions (V_CC = 5 V, T_A = 25°C). This value is specified in TI's official SN74LS112A datasheet (SCAS032H) and reflects guaranteed timing performance across the commercial temperature range. At elevated temperatures or reduced supply voltage, the usable frequency decreases due to increased propagation delay - always verify timing margins using worst-case t_PLH/t_PHL values in your specific operating environment. The SN74LS112AD does not support overclocking beyond this limit.

Does the SN74LS112AD support positive-edge clocking?

No, the SN74LS112AD is strictly a negative-edge-triggered device - its internal circuitry responds only to the falling edge of the CLK signal. Attempting to use rising-edge clocks will result in undefined or non-functional behavior. If positive-edge operation is required, consider the SN74LS76A (dual J-K master-slave with positive-edge clock) or redesign with an external inverter on the clock path. The SN74LS112AD's datasheet explicitly defines CLK as "clock (negative-edge triggered)" in all pin descriptions and timing diagrams.

Can SN74LS112AD be used in place of SN74LS76A?

No, SN74LS112AD and SN74LS76A are not interchangeable. While both are dual J-K flip-flops, SN74LS76A uses positive-edge triggering and includes complementary outputs only on Q (not Q̅), whereas SN74LS112AD uses negative-edge triggering and provides true/complement outputs on every section (Q and Q̅). Their pinouts differ significantly - for example, SN74LS76A places CLR on Pin 4 and PRE on Pin 12, while SN74LS112AD assigns CLR to Pin 1 and PRE to Pin 5. Substituting them without schematic and layout revision will cause functional failure. The SN74LS112AD must be used only where negative-edge behavior and full complementary outputs are required.

Is SN74LS112AD RoHS compliant?

Yes, the SN74LS112AD is RoHS compliant, as confirmed by Texas Instruments' official packaging documentation: it features NiPdAu (NIPDAU) lead finish and carries a "Yes" RoHS status in TI's package addendum. However, note that RoHS compliance applies only to the SN74LS112AD variant - older military or ceramic-packaged versions (e.g., JM38510/07102BEA) are exempt and contain lead. Always verify the exact orderable part number and date code when sourcing, as TI maintains separate compliance tracking per package type and manufacturing lot.

What is the purpose of the Q̅ output on SN74LS112AD?

The Q̅ output on SN74LS112AD provides the logical inverse of the Q output for each flip-flop section, eliminating the need for external inverters in applications requiring both true and complement signals - such as differential bus drivers, toggle-mode counters, or set-reset latches. In the SN74LS112AD, Q̅ is actively driven (not open-collector), matches Q in propagation delay (±1 ns), and maintains full TTL voltage levels. This dual-output architecture reduces component count and improves timing predictability compared to single-output alternatives like the SN74LS74A. The SN74LS112AD's Q̅ output is fully specified in its DC and AC characteristics tables.

SN74LS112AD Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 45 MHz

Max Propagation Delay @ V, Max CL:: 20ns @ 5V, 15pF

Trigger Type:: Negative Edge

Current - Output High, Low:: 400µA, 8mA

Voltage - Supply:: 4.75V ~ 5.25V

Current - Quiescent (Iq):: 6 mA

Input Capacitance:: -

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74LS112AD FAQ

1.How can I place an order for SN74LS112AD through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS112AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS112AD reliable?

The price and inventory of SN74LS112AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS112AD is usually 5 days.

3.What payment methods are accepted for SN74LS112AD?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS112AD transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS112AD?

SN74LS112AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS112AD order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS112AD?

For technical support, including SN74LS112AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS112AD requirements.

6.How does Aetrix verify that SN74LS112AD is sourced from the original manufacturer or authorized distributors?

All SN74LS112AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS112AD meets industry standards.

7.What is the process for return or replacement of SN74LS112AD?

All SN74LS112AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS112AD, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS112AD part is unused and in its original packaging.

Return procedure for SN74LS112AD:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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