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Home > Products > Integrated Circuits (ICs) > Logic > Flip Flops

Texas Instruments SN74LS112ADR

Name: SN74LS112ADR
Brand: Texas Instruments
SKU: SN74LS112ADR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS112ADR

Manufacturer:: Texas Instruments

Category:: Flip Flops

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74LS112ADR.pdf

Description:: IC FF JK TYPE DUAL 1BIT 16SOIC

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SN74LS112ADR from Texas Instruments is a dual J-K negative-edge-triggered flip-flop in 16-pin SOIC package, operating from 4.75 V to 5.25 V supply, with typical propagation delay of 15 ns and maximum clock frequency of 30 MHz. It features complementary Q and Q̅ outputs, individual preset and clear inputs, and is used in synchronous logic control, state machines, and digital counters.

For engineers reviewing the SN74LS112ADR datasheet, SN74LS112ADR pinout, SN74LS112ADR application, or SN74LS112ADR equivalent, key selection criteria include its TTL-compatible input thresholds, guaranteed negative-edge triggering behavior, dual independent flip-flop architecture, and industrial temperature range (0°C to 70°C) with RoHS-compliant NiPdAu lead finish.

Technical Context

The SN74LS112ADR implements two identical, independently controlled J-K flip-flops with asynchronous active-low preset (PR̅) and clear (CLR̅) inputs. Each section operates on the falling edge of the clock (CLK), ensuring deterministic state transitions synchronized to system timing edges.

Its internal structure uses bipolar TTL circuitry with Schottky-clamped transistors to achieve speed-power trade-offs typical of the LS family: fan-out of 20 TTL loads, input clamp diodes for transient protection, and output drive capability of –0.4 mA (high) and 8 mA (low) at V_CC = 5 V.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	LS-TTL - ensures compatibility with legacy 74-series systems and predictable noise margins.
Supply Voltage	4.75 V to 5.25 V - requires stable +5 V rail; no operation outside this window.
Max Clock Frequency	30 MHz - supports medium-speed sequential logic up to 33 ns minimum clock period.
Propagation Delay	15 ns (typical, CLK to Q) - defines worst-case timing budget for critical path analysis.
Output Drive	–0.4 mA (VOH), 8 mA (VOL) - sufficient to drive 20 standard TTL inputs directly.
Operating Temperature	0°C to 70°C - qualified for commercial-grade embedded and instrumentation applications.
Package	SOIC-16 (D) - surface-mount, 150 mil width, tape-and-reel (2500 pcs), MSL Level-1.

Pinout & Package

SN74LS112ADR is housed in a 16-pin Small Outline Integrated Circuit (SOIC) package (drawing D), 7.5 mm wide, 10.3 mm long, 2.0 mm max height, with 1.27 mm pitch and NiPdAu lead finish. Pin 1 is located at the top-left corner with notch or dot marking.

Pin/Terminal	Circuit Role	Design Meaning
1 (1PR̅)	Asynchronous Preset (Channel 1)	Active-low: forces Q1 = 1, Q̅1 = 0 regardless of clock or J/K state.
2 (1J)	Data Input J (Channel 1)	Sets next-state logic high when CLK falls and K = 0; enables toggle when J = K = 1.
3 (1CLK)	Clock Input (Channel 1)	Negative-edge triggered: state update occurs only on falling transition.
4 (1K)	Data Input K (Channel 1)	Resets next-state logic low when CLK falls and J = 0; enables toggle when J = K = 1.
5 (1CLR̅)	Asynchronous Clear (Channel 1)	Active-low: forces Q1 = 0, Q̅1 = 1 regardless of clock or J/K state.
6 (1Q̅)	Inverted Output (Channel 1)	Complementary to Q1; provides direct access to inverted state for feedback or decoding.
7 (GND)	Ground Reference	Return path for all internal currents; must be low-impedance and decoupled near device.
8 (2Q̅)	Inverted Output (Channel 2)	Complementary to Q2; electrically isolated from Channel 1 except shared power pins.
9 (2CLR̅)	Asynchronous Clear (Channel 2)	Independent control: clears only Q2/Q̅2 without affecting Channel 1.
10 (2K)	Data Input K (Channel 2)	Functionally identical to Pin 4 but for second flip-flop; no cross-channel coupling.
11 (2CLK)	Clock Input (Channel 2)	Falling-edge sensitive; timing independence allows dual-clock domain use with proper skew management.
12 (2J)	Data Input J (Channel 2)	Independent data path; supports separate J-K configurations per channel.
13 (2PR̅)	Asynchronous Preset (Channel 2)	Independent preset control; avoids global reset in multi-stage pipeline designs.
14 (V_CC)	Positive Supply	+5 V nominal; requires local 0.1 µF ceramic bypass capacitor between Pins 14 and 7.
15 (1Q)	True Output (Channel 1)	Main state output; drives downstream logic or bus lines within fan-out limits.
16 (2Q)	True Output (Channel 2)	Second independent output; enables compact dual-bit storage without external gating.

Key Features

Feature	Design Value
Dual independent J-K flip-flops	Enables two-bit synchronous state storage in single IC, reducing board space vs discrete solutions.
Negative-edge clocking	Eliminates setup/hold timing conflicts with rising-edge controllers; simplifies clock tree design.
Asynchronous preset/clear per channel	Allows individual initialization or fault recovery without halting entire logic block.
TTL-compatible input thresholds	V_IL ≤ 0.8 V and V_IH ≥ 2.0 V ensure reliable interfacing with standard 74-series and microcontroller GPIOs.
SOIC-16 RoHS-compliant packaging	Supports automated SMT assembly, reflow compatibility (Level-1, 260°C), and traceable sourcing.

Applications

Binary Counter Stage	State Machine Register
Use Scenario: Used as a divide-by-2 stage in a cascaded 4-bit binary counter driving LED displays or frequency dividers. IC Role / Device Role / Timing Role: Acts as a synchronous toggle element where J = K = 1, clocked by the previous stage's Q output. Use Value: Provides deterministic 50% duty-cycle output with minimal propagation skew between stages due to matched internal delays.	Use Scenario: Stores current state in a 3-state traffic light controller implemented with discrete combinational logic. IC Role / Device Role / Timing Role: Holds encoded state bits (e.g., Red=00, Yellow=01, Green=10) updated synchronously on each system clock edge. Use Value: Enables glitch-free state transitions via edge-triggered update, avoiding race conditions common in latch-based designs.
Shift Register Bit Cell	Glitch-Free Toggle Switch Debounce
Use Scenario: Forms one bit of a 16-bit serial-in/parallel-out shift register for sensor data acquisition. IC Role / Device Role / Timing Role: Captures serial data on falling clock edges and holds value until next shift pulse. Use Value: Dual flip-flop structure allows interleaved loading and shifting without external multiplexing.	Use Scenario: Debounces mechanical push-button inputs in industrial HMI panels where contact bounce exceeds 10 ms. IC Role / Device Role / Timing Role: Configured as a toggle flip-flop (J=K=1) clocked by a clean 100 Hz oscillator derived from system crystal. Use Value: Eliminates false triggers by requiring two consecutive stable samples before output change - inherent to J-K toggle behavior.

Binary Counter Stage

State Machine Register

Use Scenario: Used as a divide-by-2 stage in a cascaded 4-bit binary counter driving LED displays or frequency dividers.

IC Role / Device Role / Timing Role: Acts as a synchronous toggle element where J = K = 1, clocked by the previous stage's Q output.

Use Value: Provides deterministic 50% duty-cycle output with minimal propagation skew between stages due to matched internal delays.

Use Scenario: Stores current state in a 3-state traffic light controller implemented with discrete combinational logic.

IC Role / Device Role / Timing Role: Holds encoded state bits (e.g., Red=00, Yellow=01, Green=10) updated synchronously on each system clock edge.

Use Value: Enables glitch-free state transitions via edge-triggered update, avoiding race conditions common in latch-based designs.

Shift Register Bit Cell

Glitch-Free Toggle Switch Debounce

Use Scenario: Forms one bit of a 16-bit serial-in/parallel-out shift register for sensor data acquisition.

IC Role / Device Role / Timing Role: Captures serial data on falling clock edges and holds value until next shift pulse.

Use Value: Dual flip-flop structure allows interleaved loading and shifting without external multiplexing.

Use Scenario: Debounces mechanical push-button inputs in industrial HMI panels where contact bounce exceeds 10 ms.

IC Role / Device Role / Timing Role: Configured as a toggle flip-flop (J=K=1) clocked by a clean 100 Hz oscillator derived from system crystal.

Use Value: Eliminates false triggers by requiring two consecutive stable samples before output change - inherent to J-K toggle behavior.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual J-K flip-flop applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS76AN	Same logic function but includes complementary clock enable (CE) input per section; PDIP-16 only.	Preferred when gated clocking is required to pause state updates without disrupting preset/clear functionality.	Select SN74LS76AN if system-level clock gating is needed; otherwise SN74LS112ADR offers simpler control interface.
SN74HC112DR	CMOS version: wider V_CC range (2 V–6 V), lower I_CC, higher f_max (40 MHz), but non-TTL input thresholds.	Suitable for mixed-voltage systems or battery-powered designs where power efficiency outweighs TTL compatibility needs.	Choose SN74HC112DR for low-power or wide-supply applications; retain SN74LS112ADR for strict 5 V TTL interoperability.

Compared with SN74LS76AN and SN74HC112DR, the SN74LS112ADR delivers deterministic TTL-level timing and drive strength ideal for legacy 74-series upgrades, while avoiding CMOS input sensitivity and enabling direct drop-in replacement in existing SOIC footprints.

Availability

SN74LS112ADR is available at Aetrix Electronics and suitable for industrial control panels, test equipment interfaces, and legacy system repairs requiring stable component supply and long-term obsolescence mitigation.

Supply support for SN74LS112ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and aerospace qualification.

The SN74LS112ADR belongs to TI's legacy 74LS logic family, designed specifically for robust, medium-speed digital control in commercial-grade systems where TTL compatibility, predictable timing, and field-proven reliability are essential.

FAQ

What is the maximum clock frequency supported by SN74LS112ADR?

The SN74LS112ADR supports a maximum clock frequency of 30 MHz under standard conditions (V_CC = 5 V, T_A = 25°C). This corresponds to a minimum clock period of 33 ns, with typical propagation delay from CLK to Q of 15 ns. System-level timing must account for setup/hold times of 20 ns (J/K to CLK) and 5 ns (CLK to Q valid), as specified in the official TI datasheet.

Does SN74LS112ADR support asynchronous reset and set operations?

Yes, SN74LS112ADR provides fully independent asynchronous preset (PR̅) and clear (CLR̅) inputs for each of its two J-K flip-flops. These inputs are active-low and override clock and data signals, forcing Q = 1 or Q = 0 respectively regardless of J/K states or clock edge timing. Both functions operate with guaranteed response time under 15 ns.

Can SN74LS112ADR be used in place of SN74LS112AN?

Yes, SN74LS112ADR can replace SN74LS112AN in most designs, as both share identical logic functionality, DC electrical characteristics, and AC timing parameters. The primary difference is packaging: SN74LS112ADR uses SOIC-16 (surface-mount), while SN74LS112AN uses PDIP-16 (through-hole). PCB layout and assembly process must be adapted accordingly.

What is the recommended bypass capacitor for SN74LS112ADR?

Texas Instruments recommends a 0.1 µF ceramic capacitor placed as close as possible between V_CC (Pin 14) and GND (Pin 7) of SN74LS112ADR to suppress high-frequency supply noise. For systems with heavy switching loads, adding a bulk 10 µF tantalum or aluminum electrolytic capacitor nearby further stabilizes the +5 V rail and prevents voltage droop during simultaneous output transitions.

Is SN74LS112ADR RoHS compliant?

Yes, SN74LS112ADR is RoHS compliant, with NiPdAu (nickel-palladium-gold) lead finish and no lead (Pb)-containing solder. It meets EU Directive 2011/65/EU requirements and carries the "RoHS Yes" designation in TI's official packaging documentation. The device is rated MSL Level-1 with unlimited floor life under standard storage conditions.

SN74LS112ADR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Function:: Set(Preset) and Reset

Type:: JK Type

Output Type:: Complementary

Number of Elements:: 2

Number of Bits per Element:: 1

Clock Frequency:: 45 MHz

Max Propagation Delay @ V, Max CL:: 20ns @ 5V, 15pF

Trigger Type:: Negative Edge

Current - Output High, Low:: 400µA, 8mA

Voltage - Supply:: 4.75V ~ 5.25V

Current - Quiescent (Iq):: 6 mA

Input Capacitance:: -

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74LS112ADR FAQ

1.How can I place an order for SN74LS112ADR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS112ADR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS112ADR reliable?

The price and inventory of SN74LS112ADR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS112ADR is usually 5 days.

3.What payment methods are accepted for SN74LS112ADR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS112ADR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS112ADR?

SN74LS112ADR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS112ADR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS112ADR?

For technical support, including SN74LS112ADR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS112ADR requirements.

6.How does Aetrix verify that SN74LS112ADR is sourced from the original manufacturer or authorized distributors?

All SN74LS112ADR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS112ADR meets industry standards.

7.What is the process for return or replacement of SN74LS112ADR?

All SN74LS112ADR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS112ADR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS112ADR part is unused and in its original packaging.

Return procedure for SN74LS112ADR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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