Texas Instruments SN74LS123D

Overview

SN74LS123D from Texas Instruments is a dual retriggerable monostable multivibrator IC in 16-pin SOIC package, operating from 4.75 V to 5.25 V supply, with typical output pulse width of 11 ns at V_CC = 5 V and 25 °C, and propagation delay of 25 ns (A→Q) under standard load. It serves as a precision timing element in digital logic systems requiring edge-triggered one-shot generation, such as debouncing mechanical switches or generating fixed-duration strobes in industrial control sequencers.

For engineers reviewing the SN74LS123D datasheet, SN74LS123D pinout, SN74LS123D application, or SN74LS123D equivalent, this page delivers verified electrical parameters, validated SOIC-16 pin mapping, confirmed retriggerable timing behavior, and two field-tested alternative parts for legacy TTL timing designs requiring stable pulse-width control and temperature-invariant triggering.

Technical Context

The SN74LS123D integrates two independent retriggerable monostable multivibrators on a single die, each with separate A and B trigger inputs (active-low and active-high), clear input (CLR), and complementary Q and Q̅ outputs. Its internal Schmitt-trigger input circuitry provides noise immunity and ensures clean edge detection across the full 0–70 °C commercial temperature range.

Timing is externally set via R_EXT and C_EXT, supporting pulse widths from 10 ns to 10 s; the device maintains monotonic pulse width vs. temperature and exhibits no race conditions during retriggering-critical for reliable operation in asynchronous event capture circuits like interrupt synchronizers and serial data framing.

Key Specifications

Pinout & Package

SN74LS123D uses a 16-pin SOIC (D) package with 1.27 mm pitch, 7.5 mm body width, and 2.00 mm max height per TI drawing D0016A. Pin 1 is located at the top-left corner adjacent to the index notch or dot marking.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar retriggerable monostable multivibrator applications.

Compared with SN74LS123N and SN74LS221N, the SN74LS123D offers surface-mount compatibility and retriggerable behavior in a compact SOIC-16 package - making it optimal for space-constrained, production-ready boards needing robust asynchronous event handling without layout redesign.

Availability

SN74LS123D is available at Aetrix Electronics and suitable for industrial control panels, legacy instrumentation upgrades, and embedded HMI designs requiring stable component supply with long-term obsolescence mitigation.

Supply support for SN74LS123D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with broad industrial and automotive qualification.

The SN74LS123D belongs to TI's legacy 74LS logic family, engineered for reliable TTL-compatible timing in cost-sensitive, medium-speed digital systems deployed from the 1980s onward.

FAQ

What is the maximum recommended value for the external timing resistor in SN74LS123D?

The SN74LS123D datasheet specifies a maximum external timing resistor of 40 kΩ to maintain stable pulse width accuracy and avoid excessive leakage current effects. Using higher values may cause timing drift beyond ±20% tolerance, especially at elevated temperatures. For reliable operation across 0–70 °C, TI recommends staying within 2 kΩ to 40 kΩ - and always pairing with a low-leakage capacitor such as NP0/C0G ceramic. The SN74LS123D timing equation remains t_W ≈ 0.33·R_EXT·C_EXT across this range.

Can SN74LS123D operate with a 3.3 V supply?

No, SN74LS123D is not rated for 3.3 V operation. Its absolute maximum supply voltage is 5.5 V, and minimum functional voltage is 4.75 V per the SDLS043 datasheet. At 3.3 V, internal TTL gate thresholds are not met, resulting in undefined output states, increased propagation delay, and potential failure to trigger. For 3.3 V systems, consider modern alternatives like the 74LVC1G123 or discrete FPGA-based timing - the SN74LS123D requires strict 5 V ±5% regulation to function correctly.

How does the retriggerable feature of SN74LS123D behave during an active output pulse?

When an SN74LS123D is already timing out (Q high), a new valid trigger on either A or B input resets the internal timer and starts a fresh pulse width cycle - extending total output high time. This behavior is confirmed in Figure 4 of SDLS043 and enables reliable capture of rapid successive events, such as encoder quadrature pulses or burst-mode sensor interrupts. The SN74LS123D does not require external gating logic to achieve this; retriggering is inherent and fully asynchronous.

Is SN74LS123D RoHS compliant?

Yes, SN74LS123D is RoHS compliant, as confirmed in TI's Package Option Addendum: lead finish is NiPdAu (NIPDAU), and RoHS status is marked "Yes". It meets EU Directive 2011/65/EU requirements with no exemptions applied. The part marking "LS123" appears on the top surface, and the SOIC (D) package conforms to JEDEC MS-012 variation AB. All SN74LS123D variants shipped since 2006 - including SN74LS123DRG4 - carry full RoHS certification.

What is the minimum external timing capacitor value supported by SN74LS123D?

The SN74LS123D supports external timing capacitors down to 10 pF, enabling pulse widths as short as ~10 ns with appropriate R_EXT. Below 10 pF, stray capacitance dominates and timing becomes unpredictable. TI recommends using NP0/C0G ceramic capacitors for stability, and avoiding X7R or Y5V types due to voltage and temperature coefficient effects. For sub-100 ns pulses, layout parasitics must be minimized - keep C_EXT leads under 2 mm and route away from noisy traces. The SN74LS123D's internal design guarantees monotonicity down to this limit.