Texas Instruments SN74LS123N
- Part No.:
- SN74LS123N
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74LS123N.pdf
- Description:
- IC MULTIVIBRATOR 28NS 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,590
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LS123N from Texas Instruments is a dual retriggerable monostable multivibrator IC in 16-pin PDIP packaging, operating over 0°C to 70°C, with typical propagation delay of 25 ns at VCC = 5 V and output drive capability of ±8 mA. It provides precise, edge-triggered pulse generation for timing control in legacy TTL systems.
For engineers reviewing the SN74LS123N datasheet, SN74LS123N pinout, SN74LS123N application, or SN74LS123N equivalent, this page delivers verified functional identity, confirmed package mapping (PDIP-16), validated timing parameters, and real-world use context for industrial control, instrumentation, and retro-computing design.
Technical Context
The SN74LS123N contains two independent retriggerable monostable multivibrators, each with separate A and B trigger inputs (active-low and active-high), reset input, and Q/Q̅ outputs. Its retriggerable architecture allows pulse width extension during an active output period without requiring external gating logic.
Timing is set externally via REXT and CEXT, supporting pulse widths from 30 ns to 30 s. Output stage uses standard TTL-compatible push-pull drivers with guaranteed high-level output voltage ≥2.7 V at IOH = –0.4 mA and low-level output voltage ≤0.5 V at IOL = 8 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual retriggerable monostable multivibrator - enables single-shot pulse extension on repeated triggers without resetting the timer. |
| Supply Voltage | 4.75 V to 5.25 V - compatible with standard TTL logic rails; operation outside this range not guaranteed. |
| Propagation Delay | 25 ns typical at VCC = 5 V - defines minimum achievable pulse resolution and system timing margin. |
| Output Drive | ±8 mA - supports direct interface to multiple 74LS inputs or small LEDs without buffering. |
| Operating Temperature | 0°C to 70°C - commercial-grade rating suitable for non-military embedded and lab equipment applications. |
| Package | 16-pin PDIP (N) - through-hole mounting; 0.3-inch width; RoHS-compliant NiPdAu lead finish. |
| Pulse Width Range | 30 ns to 30 s - set by external R/C network; no internal timing components required. |
Pinout & Package
SN74LS123N is housed in a 16-pin plastic dual in-line package (PDIP-N), 0.3-inch body width, with standard 0.1-inch pin pitch and through-hole mounting. Pin 1 is located at the left end of the top row, identified by a notch or dot marking.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1A, 1B | Input A and B for Channel 1 | Active-low (1A) and active-high (1B) trigger inputs - either can initiate or retrigger the monostable output. |
| 1R̅ | Reset Input (Channel 1) | Asynchronous active-low reset - forces Q1 low and terminates output pulse immediately. |
| 1Q, 1Q̅ | Complementary Outputs (Channel 1) | Standard TTL-compatible outputs - Q1 goes high for duration set by R1/C1; Q1̅ is inverted. |
| 2A, 2B | Input A and B for Channel 2 | Independent trigger pair for second monostable - identical functionality to Channel 1. |
| 2R̅ | Reset Input (Channel 2) | Asynchronous reset for Channel 2 only - no cross-channel interference. |
| 2Q, 2Q̅ | Complementary Outputs (Channel 2) | Second independent output pair - supports dual-timing functions in one IC. |
| VCC, GND | Power Supply Pins | VCC on Pin 16, GND on Pin 8 - decoupling capacitor (0.1 µF) recommended adjacent to Pin 16. |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable operation | Enables dynamic pulse width extension during active output - eliminates need for external AND/OR logic to gate new triggers. |
| Independent dual channels | Two fully isolated monostables share only VCC/GND - simplifies multi-event timing without inter-channel crosstalk. |
| Edge-triggered inputs | 1A/2A respond to falling edges; 1B/2B respond to rising edges - supports flexible signal synchronization across mixed-edge systems. |
| External timing control | REXT/CEXT network sets pulse width - allows precise, temperature-stable timing without trimming or calibration. |
| TTL-compatible I/O | Meets LS-TTL voltage thresholds and drive strength - interoperable with 74LS, 74S, and 74F families without level-shifting. |
Applications
| Industrial Timing Control | Legacy System Glue Logic |
|---|---|
|
Use Scenario: Generating fixed-duration enable pulses for stepper motor drivers in CNC motion controllers. IC Role / Device Role / Timing Role: Monostable channel provides clean, jitter-free gate signals synchronized to step-clock edges. Use Value: Retriggerability prevents missed steps during rapid direction reversals by extending pulse width on consecutive triggers. |
Use Scenario: Debouncing mechanical switch inputs in panel-mounted test equipment front-ends. IC Role / Device Role / Timing Role: One-shot generates stable 10–100 ms clean-up window after switch closure/opening. Use Value: Dual-channel design allows simultaneous debounce of Start/Stop buttons without additional ICs. |
| Data Acquisition Trigger Conditioning | Retrocomputing Peripheral Interface |
|
Use Scenario: Converting asynchronous sensor interrupt signals into synchronized, fixed-width strobes for ADC sampling control. IC Role / Device Role / Timing Role: Acts as timing conditioner between event-driven sensors and clocked data capture logic. Use Value: External R/C tuning enables precise match to ADC conversion time, eliminating race conditions. |
Use Scenario: Implementing cartridge slot access timing windows and bus arbitration delays in 1980s-style home computer expansions. IC Role / Device Role / Timing Role: Generates memory-mapped I/O strobe delays and peripheral handshake intervals. Use Value: PDIP-16 package and TTL compatibility ensure drop-in replacement in original PCB layouts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS123DR | SOIC-16 package; same electrical specs; MSL Level-1, 260°C reflow rated. | Suitable for surface-mount production; requires PCB redesign from through-hole layout. | Select when automated assembly, space constraints, or thermal cycling reliability are priorities. |
| SN74LS221N | Non-retriggerable dual monostable; 25 ns typical tPLH; identical PDIP-16 package and pinout except reset logic. | Cannot extend pulse on repeated triggers - requires external logic for retrigger behavior. | Select only if strict non-retriggerable timing is required and board space permits added gates. |
Compared with SN74LS123DR and SN74LS221N, the SN74LS123N uniquely combines retriggerable operation, through-hole mountability, and commercial-temperature LS-TTL compatibility - making it the sole choice for legacy system repair and hand-soldered prototyping where pulse extension under burst triggering is essential.
Availability
SN74LS123N is available at Aetrix Electronics and suitable for industrial timing control, legacy system maintenance, and retrocomputing hardware development requiring stable component supply and long-term obsolescence management.
Supply support for SN74LS123N includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog and logic ICs, microcontrollers, and educational technology.
The SN74LS123N belongs to TI's classic 74LS logic family, designed specifically for robust, low-power TTL-compatible timing and sequencing in industrial, test, and computing equipment from the 1970s–1990s.
FAQ
What is the maximum pulse width achievable with SN74LS123N?
The SN74LS123N supports pulse widths up to 30 seconds using external REXT and CEXT components. This is achieved with REXT ≤ 10 MΩ and CEXT ≤ 100 µF, per the SDLS043 datasheet. The upper limit is constrained by leakage current and capacitor stability-not by the SN74LS123N itself. For reliable sub-microsecond timing, values below 1 kΩ and 100 pF are recommended.
Can SN74LS123N operate with a 3.3 V supply?
No, the SN74LS123N is specified only for 4.75 V to 5.25 V operation. It is an LS-TTL device and does not guarantee correct function or timing at 3.3 V. Attempting 3.3 V operation may result in marginal noise margins, increased propagation delay, or failure to recognize input logic levels. For 3.3 V systems, consider modern CMOS alternatives like the 74LVC123A.
Is SN74LS123N pin-compatible with SN74LS221N?
No-while both are dual monostables in PDIP-16 packages, SN74LS123N and SN74LS221N have different pin assignments. Specifically, SN74LS221N places its reset inputs on Pins 1 and 15, whereas SN74LS123N uses Pins 3 and 13. Direct substitution without PCB modification will cause functional failure. Always verify pinout diagrams before replacement.
Does SN74LS123N require pull-up resistors on its inputs?
No-inputs 1A, 1B, 2A, 2B, 1R̅, and 2R̅ are TTL-compatible and internally biased. They accept clean logic-level signals directly. Pull-ups are unnecessary unless driving from open-collector sources or long traces susceptible to noise. In such cases, 4.7 kΩ pull-ups to VCC are sufficient and consistent with LS-TTL design practice.
What is the purpose of the dual trigger inputs (A and B) on each channel of SN74LS123N?
Each channel of the SN74LS123N provides two independent trigger inputs: A (active-low) and B (active-high). This allows flexible edge detection-either a falling edge on 1A or a rising edge on 1B initiates the monostable output. Designers can choose the input that best matches upstream signal polarity, eliminating inverters and reducing component count in timing-critical paths.
SN74LS123N Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 28 ns
- Current - Output High, Low:
- 400µA, 8mA
- Voltage - Supply:
- 4.75 V ~ 5.25 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
SN74LS123N FAQ
1.How can I place an order for SN74LS123N through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS123N on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS123N reliable?
The price and inventory of SN74LS123N are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS123N is usually 5 days.
3.What payment methods are accepted for SN74LS123N?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS123N transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS123N?
SN74LS123N orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS123N order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS123N?
For technical support, including SN74LS123N datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS123N requirements.
6.How does Aetrix verify that SN74LS123N is sourced from the original manufacturer or authorized distributors?
All SN74LS123N products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS123N meets industry standards.
7.What is the process for return or replacement of SN74LS123N?
All SN74LS123N units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS123N, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS123N part is unused and in its original packaging.
Return procedure for SN74LS123N:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LS123N Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

